xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
4*4882a593Smuzhiyunsupplies clock to various controllers within the SoC.
5*4882a593Smuzhiyun
6*4882a593SmuzhiyunRequired Properties:
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun- compatible: must be one of:
9*4882a593Smuzhiyun	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
10*4882a593Smuzhiyun	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
11*4882a593Smuzhiyun	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
12*4882a593Smuzhiyun- #clock-cells: should be 1.
13*4882a593Smuzhiyun- #reset-cells: should be 1.
14*4882a593Smuzhiyun- clocks: list of clock phandles, one for each entry in clock-names
15*4882a593Smuzhiyun- clock-names: should contain the following:
16*4882a593Smuzhiyun  * "xtal": the 24MHz system oscillator
17*4882a593Smuzhiyun  * "ddr_pll": the DDR PLL clock
18*4882a593Smuzhiyun  * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
19*4882a593Smuzhiyun
20*4882a593SmuzhiyunParent node should have the following properties :
21*4882a593Smuzhiyun- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
22*4882a593Smuzhiyun- reg: base address and size of the HHI system control register space.
23*4882a593Smuzhiyun
24*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier
25*4882a593Smuzhiyunto specify the clock which they consume. All available clocks are defined as
26*4882a593Smuzhiyunpreprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
27*4882a593Smuzhiyunused in device tree sources.
28*4882a593Smuzhiyun
29*4882a593SmuzhiyunSimilarly a preprocessor macro for each reset line is defined in
30*4882a593Smuzhiyundt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
31*4882a593Smuzhiyundevice tree sources).
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun
34*4882a593SmuzhiyunExample: Clock controller node:
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	clkc: clock-controller {
37*4882a593Smuzhiyun		compatible = "amlogic,meson8b-clkc";
38*4882a593Smuzhiyun		#clock-cells = <1>;
39*4882a593Smuzhiyun		#reset-cells = <1>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun
43*4882a593SmuzhiyunExample: UART controller node that consumes the clock generated by the clock
44*4882a593Smuzhiyun  controller:
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	uart_AO: serial@c81004c0 {
47*4882a593Smuzhiyun		compatible = "amlogic,meson-uart";
48*4882a593Smuzhiyun		reg = <0xc81004c0 0x14>;
49*4882a593Smuzhiyun		interrupts = <0 90 1>;
50*4882a593Smuzhiyun		clocks = <&clkc CLKID_CLK81>;
51*4882a593Smuzhiyun	};
52