1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Amlogic DDR Clock Controller Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Martin Blumenstingl <martin.blumenstingl@googlemail.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun enum: 15*4882a593Smuzhiyun - amlogic,meson8-ddr-clkc 16*4882a593Smuzhiyun - amlogic,meson8b-ddr-clkc 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun reg: 19*4882a593Smuzhiyun maxItems: 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun clocks: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun clock-names: 25*4882a593Smuzhiyun items: 26*4882a593Smuzhiyun - const: xtal 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun "#clock-cells": 29*4882a593Smuzhiyun const: 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunrequired: 32*4882a593Smuzhiyun - compatible 33*4882a593Smuzhiyun - reg 34*4882a593Smuzhiyun - clocks 35*4882a593Smuzhiyun - clock-names 36*4882a593Smuzhiyun - "#clock-cells" 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunadditionalProperties: false 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunexamples: 41*4882a593Smuzhiyun - | 42*4882a593Smuzhiyun ddr_clkc: clock-controller@400 { 43*4882a593Smuzhiyun compatible = "amlogic,meson8-ddr-clkc"; 44*4882a593Smuzhiyun reg = <0x400 0x20>; 45*4882a593Smuzhiyun clocks = <&xtal>; 46*4882a593Smuzhiyun clock-names = "xtal"; 47*4882a593Smuzhiyun #clock-cells = <1>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun... 51