1*4882a593SmuzhiyunAlphascale Clock Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe ACC (Alphascale Clock Controller) is responsible of choising proper 4*4882a593Smuzhiyunclock source, setting deviders and clock gates. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties for the ACC node: 7*4882a593Smuzhiyun - compatible: must be "alphascale,asm9260-clock-controller" 8*4882a593Smuzhiyun - reg: must contain the ACC register base and size 9*4882a593Smuzhiyun - #clock-cells : shall be set to 1. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunSimple one-cell clock specifier format is used, where the only cell is used 12*4882a593Smuzhiyunas an index of the clock inside the provider. 13*4882a593SmuzhiyunIt is encouraged to use dt-binding for clock index definitions. SoC specific 14*4882a593Smuzhiyundt-binding should be included to the device tree descriptor. For example 15*4882a593SmuzhiyunAlphascale ASM9260: 16*4882a593Smuzhiyun#include <dt-bindings/clock/alphascale,asm9260.h> 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunThis binding contains two types of clock providers: 19*4882a593Smuzhiyun _AHB_ - AHB gate; 20*4882a593Smuzhiyun _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider. 21*4882a593SmuzhiyunAll clock specific details can be found in the SoC documentation. 22*4882a593SmuzhiyunCLKID_AHB_ROM 0 23*4882a593SmuzhiyunCLKID_AHB_RAM 1 24*4882a593SmuzhiyunCLKID_AHB_GPIO 2 25*4882a593SmuzhiyunCLKID_AHB_MAC 3 26*4882a593SmuzhiyunCLKID_AHB_EMI 4 27*4882a593SmuzhiyunCLKID_AHB_USB0 5 28*4882a593SmuzhiyunCLKID_AHB_USB1 6 29*4882a593SmuzhiyunCLKID_AHB_DMA0 7 30*4882a593SmuzhiyunCLKID_AHB_DMA1 8 31*4882a593SmuzhiyunCLKID_AHB_UART0 9 32*4882a593SmuzhiyunCLKID_AHB_UART1 10 33*4882a593SmuzhiyunCLKID_AHB_UART2 11 34*4882a593SmuzhiyunCLKID_AHB_UART3 12 35*4882a593SmuzhiyunCLKID_AHB_UART4 13 36*4882a593SmuzhiyunCLKID_AHB_UART5 14 37*4882a593SmuzhiyunCLKID_AHB_UART6 15 38*4882a593SmuzhiyunCLKID_AHB_UART7 16 39*4882a593SmuzhiyunCLKID_AHB_UART8 17 40*4882a593SmuzhiyunCLKID_AHB_UART9 18 41*4882a593SmuzhiyunCLKID_AHB_I2S0 19 42*4882a593SmuzhiyunCLKID_AHB_I2C0 20 43*4882a593SmuzhiyunCLKID_AHB_I2C1 21 44*4882a593SmuzhiyunCLKID_AHB_SSP0 22 45*4882a593SmuzhiyunCLKID_AHB_IOCONFIG 23 46*4882a593SmuzhiyunCLKID_AHB_WDT 24 47*4882a593SmuzhiyunCLKID_AHB_CAN0 25 48*4882a593SmuzhiyunCLKID_AHB_CAN1 26 49*4882a593SmuzhiyunCLKID_AHB_MPWM 27 50*4882a593SmuzhiyunCLKID_AHB_SPI0 28 51*4882a593SmuzhiyunCLKID_AHB_SPI1 29 52*4882a593SmuzhiyunCLKID_AHB_QEI 30 53*4882a593SmuzhiyunCLKID_AHB_QUADSPI0 31 54*4882a593SmuzhiyunCLKID_AHB_CAMIF 32 55*4882a593SmuzhiyunCLKID_AHB_LCDIF 33 56*4882a593SmuzhiyunCLKID_AHB_TIMER0 34 57*4882a593SmuzhiyunCLKID_AHB_TIMER1 35 58*4882a593SmuzhiyunCLKID_AHB_TIMER2 36 59*4882a593SmuzhiyunCLKID_AHB_TIMER3 37 60*4882a593SmuzhiyunCLKID_AHB_IRQ 38 61*4882a593SmuzhiyunCLKID_AHB_RTC 39 62*4882a593SmuzhiyunCLKID_AHB_NAND 40 63*4882a593SmuzhiyunCLKID_AHB_ADC0 41 64*4882a593SmuzhiyunCLKID_AHB_LED 42 65*4882a593SmuzhiyunCLKID_AHB_DAC0 43 66*4882a593SmuzhiyunCLKID_AHB_LCD 44 67*4882a593SmuzhiyunCLKID_AHB_I2S1 45 68*4882a593SmuzhiyunCLKID_AHB_MAC1 46 69*4882a593Smuzhiyun 70*4882a593SmuzhiyunCLKID_SYS_CPU 47 71*4882a593SmuzhiyunCLKID_SYS_AHB 48 72*4882a593SmuzhiyunCLKID_SYS_I2S0M 49 73*4882a593SmuzhiyunCLKID_SYS_I2S0S 50 74*4882a593SmuzhiyunCLKID_SYS_I2S1M 51 75*4882a593SmuzhiyunCLKID_SYS_I2S1S 52 76*4882a593SmuzhiyunCLKID_SYS_UART0 53 77*4882a593SmuzhiyunCLKID_SYS_UART1 54 78*4882a593SmuzhiyunCLKID_SYS_UART2 55 79*4882a593SmuzhiyunCLKID_SYS_UART3 56 80*4882a593SmuzhiyunCLKID_SYS_UART4 56 81*4882a593SmuzhiyunCLKID_SYS_UART5 57 82*4882a593SmuzhiyunCLKID_SYS_UART6 58 83*4882a593SmuzhiyunCLKID_SYS_UART7 59 84*4882a593SmuzhiyunCLKID_SYS_UART8 60 85*4882a593SmuzhiyunCLKID_SYS_UART9 61 86*4882a593SmuzhiyunCLKID_SYS_SPI0 62 87*4882a593SmuzhiyunCLKID_SYS_SPI1 63 88*4882a593SmuzhiyunCLKID_SYS_QUADSPI 64 89*4882a593SmuzhiyunCLKID_SYS_SSP0 65 90*4882a593SmuzhiyunCLKID_SYS_NAND 66 91*4882a593SmuzhiyunCLKID_SYS_TRACE 67 92*4882a593SmuzhiyunCLKID_SYS_CAMM 68 93*4882a593SmuzhiyunCLKID_SYS_WDT 69 94*4882a593SmuzhiyunCLKID_SYS_CLKOUT 70 95*4882a593SmuzhiyunCLKID_SYS_MAC 71 96*4882a593SmuzhiyunCLKID_SYS_LCD 72 97*4882a593SmuzhiyunCLKID_SYS_ADCANA 73 98*4882a593Smuzhiyun 99*4882a593SmuzhiyunExample of clock consumer with _SYS_ and _AHB_ sinks. 100*4882a593Smuzhiyunuart4: serial@80010000 { 101*4882a593Smuzhiyun compatible = "alphascale,asm9260-uart"; 102*4882a593Smuzhiyun reg = <0x80010000 0x4000>; 103*4882a593Smuzhiyun clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>; 104*4882a593Smuzhiyun interrupts = <19>; 105*4882a593Smuzhiyun}; 106*4882a593Smuzhiyun 107*4882a593SmuzhiyunClock consumer with only one, _AHB_ sink. 108*4882a593Smuzhiyuntimer0: timer@80088000 { 109*4882a593Smuzhiyun compatible = "alphascale,asm9260-timer"; 110*4882a593Smuzhiyun reg = <0x80088000 0x4000>; 111*4882a593Smuzhiyun clocks = <&acc CLKID_AHB_TIMER0>; 112*4882a593Smuzhiyun interrupts = <29>; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115