1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A80 MMC Configuration Clock Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundeprecated: true
14*4882a593Smuzhiyun
15*4882a593Smuzhiyundescription: >
16*4882a593Smuzhiyun  There is one clock/reset output per mmc controller. The number of
17*4882a593Smuzhiyun  outputs is determined by the size of the address block, which is
18*4882a593Smuzhiyun  related to the overall mmc block.
19*4882a593Smuzhiyun
20*4882a593Smuzhiyunproperties:
21*4882a593Smuzhiyun  "#clock-cells":
22*4882a593Smuzhiyun    const: 1
23*4882a593Smuzhiyun    description: >
24*4882a593Smuzhiyun      The additional ID argument passed to the clock shall refer to
25*4882a593Smuzhiyun      the index of the output.
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  "#reset-cells":
28*4882a593Smuzhiyun    const: 1
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun  compatible:
31*4882a593Smuzhiyun    const: allwinner,sun9i-a80-mmc-config-clk
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  reg:
34*4882a593Smuzhiyun    maxItems: 1
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun  clocks:
37*4882a593Smuzhiyun    maxItems: 1
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun  resets:
40*4882a593Smuzhiyun    maxItems: 1
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun  clock-output-names:
43*4882a593Smuzhiyun    maxItems: 4
44*4882a593Smuzhiyun
45*4882a593Smuzhiyunrequired:
46*4882a593Smuzhiyun  - "#clock-cells"
47*4882a593Smuzhiyun  - "#reset-cells"
48*4882a593Smuzhiyun  - compatible
49*4882a593Smuzhiyun  - reg
50*4882a593Smuzhiyun  - clocks
51*4882a593Smuzhiyun  - clock-output-names
52*4882a593Smuzhiyun
53*4882a593SmuzhiyunadditionalProperties: false
54*4882a593Smuzhiyun
55*4882a593Smuzhiyunexamples:
56*4882a593Smuzhiyun  - |
57*4882a593Smuzhiyun    clk@1c13000 {
58*4882a593Smuzhiyun        #clock-cells = <1>;
59*4882a593Smuzhiyun        #reset-cells = <1>;
60*4882a593Smuzhiyun        compatible = "allwinner,sun9i-a80-mmc-config-clk";
61*4882a593Smuzhiyun        reg = <0x01c13000 0x10>;
62*4882a593Smuzhiyun        clocks = <&ahb0_gates 8>;
63*4882a593Smuzhiyun        resets = <&ahb0_resets 8>;
64*4882a593Smuzhiyun        clock-output-names = "mmc0_config", "mmc1_config",
65*4882a593Smuzhiyun                             "mmc2_config", "mmc3_config";
66*4882a593Smuzhiyun    };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun...
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