1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A80 Display Engine Clock Controller Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun "#clock-cells": 15*4882a593Smuzhiyun const: 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun "#reset-cells": 18*4882a593Smuzhiyun const: 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun const: allwinner,sun9i-a80-de-clks 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks: 27*4882a593Smuzhiyun items: 28*4882a593Smuzhiyun - description: Bus Clock 29*4882a593Smuzhiyun - description: RAM Bus Clock 30*4882a593Smuzhiyun - description: Module Clock 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clock-names: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - const: mod 35*4882a593Smuzhiyun - const: dram 36*4882a593Smuzhiyun - const: bus 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun resets: 39*4882a593Smuzhiyun maxItems: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunrequired: 42*4882a593Smuzhiyun - "#clock-cells" 43*4882a593Smuzhiyun - "#reset-cells" 44*4882a593Smuzhiyun - compatible 45*4882a593Smuzhiyun - reg 46*4882a593Smuzhiyun - clocks 47*4882a593Smuzhiyun - clock-names 48*4882a593Smuzhiyun - resets 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunadditionalProperties: false 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunexamples: 53*4882a593Smuzhiyun - | 54*4882a593Smuzhiyun #include <dt-bindings/clock/sun9i-a80-ccu.h> 55*4882a593Smuzhiyun #include <dt-bindings/reset/sun9i-a80-ccu.h> 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun de_clocks: clock@3000000 { 58*4882a593Smuzhiyun compatible = "allwinner,sun9i-a80-de-clks"; 59*4882a593Smuzhiyun reg = <0x03000000 0x30>; 60*4882a593Smuzhiyun clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; 61*4882a593Smuzhiyun clock-names = "mod", "dram", "bus"; 62*4882a593Smuzhiyun resets = <&ccu RST_BUS_DE>; 63*4882a593Smuzhiyun #clock-cells = <1>; 64*4882a593Smuzhiyun #reset-cells = <1>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun... 68