1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A20 GMAC TX Clock Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun "#clock-cells": 15*4882a593Smuzhiyun const: 0 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: allwinner,sun7i-a20-gmac-clk 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun clocks: 24*4882a593Smuzhiyun maxItems: 2 25*4882a593Smuzhiyun description: > 26*4882a593Smuzhiyun The parent clocks shall be fixed rate dummy clocks at 25 MHz and 27*4882a593Smuzhiyun 125 MHz, respectively. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clock-output-names: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunrequired: 33*4882a593Smuzhiyun - "#clock-cells" 34*4882a593Smuzhiyun - compatible 35*4882a593Smuzhiyun - reg 36*4882a593Smuzhiyun - clocks 37*4882a593Smuzhiyun - clock-output-names 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunadditionalProperties: false 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunexamples: 42*4882a593Smuzhiyun - | 43*4882a593Smuzhiyun clk@1c20164 { 44*4882a593Smuzhiyun #clock-cells = <0>; 45*4882a593Smuzhiyun compatible = "allwinner,sun7i-a20-gmac-clk"; 46*4882a593Smuzhiyun reg = <0x01c20164 0x4>; 47*4882a593Smuzhiyun clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 48*4882a593Smuzhiyun clock-output-names = "gmac_tx"; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun... 52