1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A10 CPU PLL Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundeprecated: true 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun "#clock-cells": 17*4882a593Smuzhiyun const: 0 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun enum: 21*4882a593Smuzhiyun - allwinner,sun4i-a10-pll1-clk 22*4882a593Smuzhiyun - allwinner,sun6i-a31-pll1-clk 23*4882a593Smuzhiyun - allwinner,sun8i-a23-pll1-clk 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clocks: 29*4882a593Smuzhiyun maxItems: 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun clock-output-names: 32*4882a593Smuzhiyun maxItems: 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyunrequired: 35*4882a593Smuzhiyun - "#clock-cells" 36*4882a593Smuzhiyun - compatible 37*4882a593Smuzhiyun - reg 38*4882a593Smuzhiyun - clocks 39*4882a593Smuzhiyun - clock-output-names 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunadditionalProperties: false 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunexamples: 44*4882a593Smuzhiyun - | 45*4882a593Smuzhiyun clk@1c20000 { 46*4882a593Smuzhiyun #clock-cells = <0>; 47*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-pll1"; 48*4882a593Smuzhiyun reg = <0x01c20000 0x4>; 49*4882a593Smuzhiyun clocks = <&osc24M>; 50*4882a593Smuzhiyun clock-output-names = "osc24M"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun - | 54*4882a593Smuzhiyun clk@1c20000 { 55*4882a593Smuzhiyun #clock-cells = <0>; 56*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-pll1-clk"; 57*4882a593Smuzhiyun reg = <0x01c20000 0x4>; 58*4882a593Smuzhiyun clocks = <&osc24M>; 59*4882a593Smuzhiyun clock-output-names = "pll1"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun - | 63*4882a593Smuzhiyun clk@1c20000 { 64*4882a593Smuzhiyun #clock-cells = <0>; 65*4882a593Smuzhiyun compatible = "allwinner,sun8i-a23-pll1-clk"; 66*4882a593Smuzhiyun reg = <0x01c20000 0x4>; 67*4882a593Smuzhiyun clocks = <&osc24M>; 68*4882a593Smuzhiyun clock-output-names = "pll1"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun... 72