1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A10 Module 0 Clock Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundeprecated: true 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunselect: 16*4882a593Smuzhiyun properties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun contains: 19*4882a593Smuzhiyun enum: 20*4882a593Smuzhiyun - allwinner,sun4i-a10-mod0-clk 21*4882a593Smuzhiyun - allwinner,sun9i-a80-mod0-clk 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun # The PRCM on the A31 and A23 will have the reg property missing, 24*4882a593Smuzhiyun # since it's set at the upper level node, and will be validated by 25*4882a593Smuzhiyun # PRCM's schema. Make sure we only validate standalone nodes. 26*4882a593Smuzhiyun required: 27*4882a593Smuzhiyun - compatible 28*4882a593Smuzhiyun - reg 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunproperties: 31*4882a593Smuzhiyun "#clock-cells": 32*4882a593Smuzhiyun const: 0 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun compatible: 35*4882a593Smuzhiyun enum: 36*4882a593Smuzhiyun - allwinner,sun4i-a10-mod0-clk 37*4882a593Smuzhiyun - allwinner,sun9i-a80-mod0-clk 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun reg: 40*4882a593Smuzhiyun maxItems: 1 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun clocks: 43*4882a593Smuzhiyun # On the A80, the PRCM mod0 clocks have 2 parents. 44*4882a593Smuzhiyun minItems: 2 45*4882a593Smuzhiyun maxItems: 3 46*4882a593Smuzhiyun description: > 47*4882a593Smuzhiyun The parent order must match the hardware programming order. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun clock-output-names: 50*4882a593Smuzhiyun maxItems: 1 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunrequired: 53*4882a593Smuzhiyun - "#clock-cells" 54*4882a593Smuzhiyun - compatible 55*4882a593Smuzhiyun - reg 56*4882a593Smuzhiyun - clocks 57*4882a593Smuzhiyun - clock-output-names 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunadditionalProperties: false 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunexamples: 62*4882a593Smuzhiyun - | 63*4882a593Smuzhiyun clk@1c20080 { 64*4882a593Smuzhiyun #clock-cells = <0>; 65*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-mod0-clk"; 66*4882a593Smuzhiyun reg = <0x01c20080 0x4>; 67*4882a593Smuzhiyun clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 68*4882a593Smuzhiyun clock-output-names = "nand"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun - | 72*4882a593Smuzhiyun clk@8001454 { 73*4882a593Smuzhiyun #clock-cells = <0>; 74*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-mod0-clk"; 75*4882a593Smuzhiyun reg = <0x08001454 0x4>; 76*4882a593Smuzhiyun clocks = <&osc32k>, <&osc24M>; 77*4882a593Smuzhiyun clock-output-names = "r_ir"; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun... 81