xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A10 Module 1 Clock Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundeprecated: true
14*4882a593Smuzhiyun
15*4882a593Smuzhiyunproperties:
16*4882a593Smuzhiyun  "#clock-cells":
17*4882a593Smuzhiyun    const: 1
18*4882a593Smuzhiyun    description: >
19*4882a593Smuzhiyun      There is three different outputs: the main clock, with the ID 0,
20*4882a593Smuzhiyun      and the output and sample clocks, with the IDs 1 and 2,
21*4882a593Smuzhiyun      respectively.
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  compatible:
24*4882a593Smuzhiyun    enum:
25*4882a593Smuzhiyun      - allwinner,sun4i-a10-mmc-clk
26*4882a593Smuzhiyun      - allwinner,sun9i-a80-mmc-clk
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  reg:
29*4882a593Smuzhiyun    maxItems: 1
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun  clocks:
32*4882a593Smuzhiyun    minItems: 2
33*4882a593Smuzhiyun    maxItems: 3
34*4882a593Smuzhiyun    description: >
35*4882a593Smuzhiyun      The parent order must match the hardware programming order.
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  clock-output-names:
38*4882a593Smuzhiyun    maxItems: 3
39*4882a593Smuzhiyun
40*4882a593Smuzhiyunrequired:
41*4882a593Smuzhiyun  - "#clock-cells"
42*4882a593Smuzhiyun  - compatible
43*4882a593Smuzhiyun  - reg
44*4882a593Smuzhiyun  - clocks
45*4882a593Smuzhiyun  - clock-output-names
46*4882a593Smuzhiyun
47*4882a593SmuzhiyunadditionalProperties: false
48*4882a593Smuzhiyun
49*4882a593Smuzhiyunif:
50*4882a593Smuzhiyun  properties:
51*4882a593Smuzhiyun    compatible:
52*4882a593Smuzhiyun      contains:
53*4882a593Smuzhiyun        const: allwinner,sun4i-a10-mmc-clk
54*4882a593Smuzhiyun
55*4882a593Smuzhiyunthen:
56*4882a593Smuzhiyun  properties:
57*4882a593Smuzhiyun    clocks:
58*4882a593Smuzhiyun      maxItems: 3
59*4882a593Smuzhiyun
60*4882a593Smuzhiyunelse:
61*4882a593Smuzhiyun  properties:
62*4882a593Smuzhiyun    clocks:
63*4882a593Smuzhiyun      maxItems: 2
64*4882a593Smuzhiyun
65*4882a593Smuzhiyunexamples:
66*4882a593Smuzhiyun  - |
67*4882a593Smuzhiyun    clk@1c20088 {
68*4882a593Smuzhiyun        #clock-cells = <1>;
69*4882a593Smuzhiyun        compatible = "allwinner,sun4i-a10-mmc-clk";
70*4882a593Smuzhiyun        reg = <0x01c20088 0x4>;
71*4882a593Smuzhiyun        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
72*4882a593Smuzhiyun        clock-output-names = "mmc0",
73*4882a593Smuzhiyun                             "mmc0_output",
74*4882a593Smuzhiyun                             "mmc0_sample";
75*4882a593Smuzhiyun    };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun  - |
78*4882a593Smuzhiyun    clk@6000410 {
79*4882a593Smuzhiyun        #clock-cells = <1>;
80*4882a593Smuzhiyun        compatible = "allwinner,sun9i-a80-mmc-clk";
81*4882a593Smuzhiyun        reg = <0x06000410 0x4>;
82*4882a593Smuzhiyun        clocks = <&osc24M>, <&pll4>;
83*4882a593Smuzhiyun        clock-output-names = "mmc0", "mmc0_output",
84*4882a593Smuzhiyun                             "mmc0_sample";
85*4882a593Smuzhiyun    };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun...
88