1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A10 Bus Gates Clock Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundeprecated: true 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun "#clock-cells": 17*4882a593Smuzhiyun const: 1 18*4882a593Smuzhiyun description: > 19*4882a593Smuzhiyun This additional argument passed to that clock is the offset of 20*4882a593Smuzhiyun the bit controlling this particular gate in the register. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun compatible: 23*4882a593Smuzhiyun oneOf: 24*4882a593Smuzhiyun - const: allwinner,sun4i-a10-gates-clk 25*4882a593Smuzhiyun - const: allwinner,sun4i-a10-axi-gates-clk 26*4882a593Smuzhiyun - const: allwinner,sun4i-a10-ahb-gates-clk 27*4882a593Smuzhiyun - const: allwinner,sun5i-a10s-ahb-gates-clk 28*4882a593Smuzhiyun - const: allwinner,sun5i-a13-ahb-gates-clk 29*4882a593Smuzhiyun - const: allwinner,sun7i-a20-ahb-gates-clk 30*4882a593Smuzhiyun - const: allwinner,sun6i-a31-ahb1-gates-clk 31*4882a593Smuzhiyun - const: allwinner,sun8i-a23-ahb1-gates-clk 32*4882a593Smuzhiyun - const: allwinner,sun9i-a80-ahb0-gates-clk 33*4882a593Smuzhiyun - const: allwinner,sun9i-a80-ahb1-gates-clk 34*4882a593Smuzhiyun - const: allwinner,sun9i-a80-ahb2-gates-clk 35*4882a593Smuzhiyun - const: allwinner,sun4i-a10-apb0-gates-clk 36*4882a593Smuzhiyun - const: allwinner,sun5i-a10s-apb0-gates-clk 37*4882a593Smuzhiyun - const: allwinner,sun5i-a13-apb0-gates-clk 38*4882a593Smuzhiyun - const: allwinner,sun7i-a20-apb0-gates-clk 39*4882a593Smuzhiyun - const: allwinner,sun9i-a80-apb0-gates-clk 40*4882a593Smuzhiyun - const: allwinner,sun8i-a83t-apb0-gates-clk 41*4882a593Smuzhiyun - const: allwinner,sun4i-a10-apb1-gates-clk 42*4882a593Smuzhiyun - const: allwinner,sun5i-a13-apb1-gates-clk 43*4882a593Smuzhiyun - const: allwinner,sun5i-a10s-apb1-gates-clk 44*4882a593Smuzhiyun - const: allwinner,sun6i-a31-apb1-gates-clk 45*4882a593Smuzhiyun - const: allwinner,sun7i-a20-apb1-gates-clk 46*4882a593Smuzhiyun - const: allwinner,sun8i-a23-apb1-gates-clk 47*4882a593Smuzhiyun - const: allwinner,sun9i-a80-apb1-gates-clk 48*4882a593Smuzhiyun - const: allwinner,sun6i-a31-apb2-gates-clk 49*4882a593Smuzhiyun - const: allwinner,sun8i-a23-apb2-gates-clk 50*4882a593Smuzhiyun - const: allwinner,sun8i-a83t-bus-gates-clk 51*4882a593Smuzhiyun - const: allwinner,sun9i-a80-apbs-gates-clk 52*4882a593Smuzhiyun - const: allwinner,sun4i-a10-dram-gates-clk 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun - items: 55*4882a593Smuzhiyun - const: allwinner,sun5i-a13-dram-gates-clk 56*4882a593Smuzhiyun - const: allwinner,sun4i-a10-gates-clk 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun - items: 59*4882a593Smuzhiyun - const: allwinner,sun8i-h3-apb0-gates-clk 60*4882a593Smuzhiyun - const: allwinner,sun4i-a10-gates-clk 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun reg: 63*4882a593Smuzhiyun maxItems: 1 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun clocks: 66*4882a593Smuzhiyun maxItems: 1 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun clock-indices: 69*4882a593Smuzhiyun minItems: 1 70*4882a593Smuzhiyun maxItems: 64 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun clock-output-names: 73*4882a593Smuzhiyun minItems: 1 74*4882a593Smuzhiyun maxItems: 64 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunrequired: 77*4882a593Smuzhiyun - "#clock-cells" 78*4882a593Smuzhiyun - compatible 79*4882a593Smuzhiyun - reg 80*4882a593Smuzhiyun - clocks 81*4882a593Smuzhiyun - clock-indices 82*4882a593Smuzhiyun - clock-output-names 83*4882a593Smuzhiyun 84*4882a593SmuzhiyunadditionalProperties: false 85*4882a593Smuzhiyun 86*4882a593Smuzhiyunexamples: 87*4882a593Smuzhiyun - | 88*4882a593Smuzhiyun clk@1c2005c { 89*4882a593Smuzhiyun #clock-cells = <1>; 90*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-axi-gates-clk"; 91*4882a593Smuzhiyun reg = <0x01c2005c 0x4>; 92*4882a593Smuzhiyun clocks = <&axi>; 93*4882a593Smuzhiyun clock-indices = <0>; 94*4882a593Smuzhiyun clock-output-names = "axi_dram"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun - | 98*4882a593Smuzhiyun clk@1c20060 { 99*4882a593Smuzhiyun #clock-cells = <1>; 100*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-ahb-gates-clk"; 101*4882a593Smuzhiyun reg = <0x01c20060 0x8>; 102*4882a593Smuzhiyun clocks = <&ahb>; 103*4882a593Smuzhiyun clock-indices = <0>, <1>, 104*4882a593Smuzhiyun <2>, <3>, 105*4882a593Smuzhiyun <4>, <5>, <6>, 106*4882a593Smuzhiyun <7>, <8>, <9>, 107*4882a593Smuzhiyun <10>, <11>, <12>, 108*4882a593Smuzhiyun <13>, <14>, <16>, 109*4882a593Smuzhiyun <17>, <18>, <20>, 110*4882a593Smuzhiyun <21>, <22>, <23>, 111*4882a593Smuzhiyun <24>, <25>, <26>, 112*4882a593Smuzhiyun <32>, <33>, <34>, 113*4882a593Smuzhiyun <35>, <36>, <37>, 114*4882a593Smuzhiyun <40>, <41>, <43>, 115*4882a593Smuzhiyun <44>, <45>, 116*4882a593Smuzhiyun <46>, <47>, 117*4882a593Smuzhiyun <50>, <52>; 118*4882a593Smuzhiyun clock-output-names = "ahb_usb0", "ahb_ehci0", 119*4882a593Smuzhiyun "ahb_ohci0", "ahb_ehci1", 120*4882a593Smuzhiyun "ahb_ohci1", "ahb_ss", "ahb_dma", 121*4882a593Smuzhiyun "ahb_bist", "ahb_mmc0", "ahb_mmc1", 122*4882a593Smuzhiyun "ahb_mmc2", "ahb_mmc3", "ahb_ms", 123*4882a593Smuzhiyun "ahb_nand", "ahb_sdram", "ahb_ace", 124*4882a593Smuzhiyun "ahb_emac", "ahb_ts", "ahb_spi0", 125*4882a593Smuzhiyun "ahb_spi1", "ahb_spi2", "ahb_spi3", 126*4882a593Smuzhiyun "ahb_pata", "ahb_sata", "ahb_gps", 127*4882a593Smuzhiyun "ahb_ve", "ahb_tvd", "ahb_tve0", 128*4882a593Smuzhiyun "ahb_tve1", "ahb_lcd0", "ahb_lcd1", 129*4882a593Smuzhiyun "ahb_csi0", "ahb_csi1", "ahb_hdmi", 130*4882a593Smuzhiyun "ahb_de_be0", "ahb_de_be1", 131*4882a593Smuzhiyun "ahb_de_fe0", "ahb_de_fe1", 132*4882a593Smuzhiyun "ahb_mp", "ahb_mali400"; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun - | 137*4882a593Smuzhiyun clk@1c20068 { 138*4882a593Smuzhiyun #clock-cells = <1>; 139*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-apb0-gates-clk"; 140*4882a593Smuzhiyun reg = <0x01c20068 0x4>; 141*4882a593Smuzhiyun clocks = <&apb0>; 142*4882a593Smuzhiyun clock-indices = <0>, <1>, 143*4882a593Smuzhiyun <2>, <3>, 144*4882a593Smuzhiyun <5>, <6>, 145*4882a593Smuzhiyun <7>, <10>; 146*4882a593Smuzhiyun clock-output-names = "apb0_codec", "apb0_spdif", 147*4882a593Smuzhiyun "apb0_ac97", "apb0_iis", 148*4882a593Smuzhiyun "apb0_pio", "apb0_ir0", 149*4882a593Smuzhiyun "apb0_ir1", "apb0_keypad"; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun... 153