1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A10 Bus Gates Clock Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundeprecated: true
14*4882a593Smuzhiyun
15*4882a593Smuzhiyunproperties:
16*4882a593Smuzhiyun  "#clock-cells":
17*4882a593Smuzhiyun    const: 1
18*4882a593Smuzhiyun    description: >
19*4882a593Smuzhiyun      This additional argument passed to that clock is the offset of
20*4882a593Smuzhiyun      the bit controlling this particular gate in the register.
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun  compatible:
23*4882a593Smuzhiyun    const: allwinner,sun8i-h3-bus-gates-clk
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  reg:
26*4882a593Smuzhiyun    maxItems: 1
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  clocks:
29*4882a593Smuzhiyun    maxItems: 4
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun  clock-names:
32*4882a593Smuzhiyun    maxItems: 4
33*4882a593Smuzhiyun    description: >
34*4882a593Smuzhiyun      The parent order must match the hardware programming order.
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun  clock-indices:
37*4882a593Smuzhiyun    minItems: 1
38*4882a593Smuzhiyun    maxItems: 64
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun  clock-output-names:
41*4882a593Smuzhiyun    minItems: 1
42*4882a593Smuzhiyun    maxItems: 64
43*4882a593Smuzhiyun
44*4882a593Smuzhiyunrequired:
45*4882a593Smuzhiyun  - "#clock-cells"
46*4882a593Smuzhiyun  - compatible
47*4882a593Smuzhiyun  - reg
48*4882a593Smuzhiyun  - clocks
49*4882a593Smuzhiyun  - clock-indices
50*4882a593Smuzhiyun  - clock-names
51*4882a593Smuzhiyun  - clock-output-names
52*4882a593Smuzhiyun
53*4882a593SmuzhiyunadditionalProperties: false
54*4882a593Smuzhiyun
55*4882a593Smuzhiyunexamples:
56*4882a593Smuzhiyun  - |
57*4882a593Smuzhiyun    clk@1c20060 {
58*4882a593Smuzhiyun        #clock-cells = <1>;
59*4882a593Smuzhiyun        compatible = "allwinner,sun8i-h3-bus-gates-clk";
60*4882a593Smuzhiyun        reg = <0x01c20060 0x14>;
61*4882a593Smuzhiyun        clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
62*4882a593Smuzhiyun        clock-names = "ahb1", "ahb2", "apb1", "apb2";
63*4882a593Smuzhiyun        clock-indices = <5>, <6>, <8>,
64*4882a593Smuzhiyun                        <9>, <10>, <13>,
65*4882a593Smuzhiyun                        <14>, <17>, <18>,
66*4882a593Smuzhiyun                        <19>, <20>,
67*4882a593Smuzhiyun                        <21>, <23>,
68*4882a593Smuzhiyun                        <24>, <25>,
69*4882a593Smuzhiyun                        <26>, <27>,
70*4882a593Smuzhiyun                        <28>, <29>,
71*4882a593Smuzhiyun                        <30>, <31>, <32>,
72*4882a593Smuzhiyun                        <35>, <36>, <37>,
73*4882a593Smuzhiyun                        <40>, <41>, <43>,
74*4882a593Smuzhiyun                        <44>, <52>, <53>,
75*4882a593Smuzhiyun                        <54>, <64>,
76*4882a593Smuzhiyun                        <65>, <69>, <72>,
77*4882a593Smuzhiyun                        <76>, <77>, <78>,
78*4882a593Smuzhiyun                        <96>, <97>, <98>,
79*4882a593Smuzhiyun                        <112>, <113>,
80*4882a593Smuzhiyun                        <114>, <115>,
81*4882a593Smuzhiyun                        <116>, <128>, <135>;
82*4882a593Smuzhiyun        clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
83*4882a593Smuzhiyun                             "bus_mmc1", "bus_mmc2", "bus_nand",
84*4882a593Smuzhiyun                             "bus_sdram", "bus_gmac", "bus_ts",
85*4882a593Smuzhiyun                             "bus_hstimer", "bus_spi0",
86*4882a593Smuzhiyun                             "bus_spi1", "bus_otg",
87*4882a593Smuzhiyun                             "bus_otg_ehci0", "bus_ehci1",
88*4882a593Smuzhiyun                             "bus_ehci2", "bus_ehci3",
89*4882a593Smuzhiyun                             "bus_otg_ohci0", "bus_ohci1",
90*4882a593Smuzhiyun                             "bus_ohci2", "bus_ohci3", "bus_ve",
91*4882a593Smuzhiyun                             "bus_lcd0", "bus_lcd1", "bus_deint",
92*4882a593Smuzhiyun                             "bus_csi", "bus_tve", "bus_hdmi",
93*4882a593Smuzhiyun                             "bus_de", "bus_gpu", "bus_msgbox",
94*4882a593Smuzhiyun                             "bus_spinlock", "bus_codec",
95*4882a593Smuzhiyun                             "bus_spdif", "bus_pio", "bus_ths",
96*4882a593Smuzhiyun                             "bus_i2s0", "bus_i2s1", "bus_i2s2",
97*4882a593Smuzhiyun                             "bus_i2c0", "bus_i2c1", "bus_i2c2",
98*4882a593Smuzhiyun                             "bus_uart0", "bus_uart1",
99*4882a593Smuzhiyun                             "bus_uart2", "bus_uart3",
100*4882a593Smuzhiyun                             "bus_scr", "bus_ephy", "bus_dbg";
101*4882a593Smuzhiyun    };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun...
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