1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A83t Display Engine 2/3 Clock Controller Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun "#clock-cells": 15*4882a593Smuzhiyun const: 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun "#reset-cells": 18*4882a593Smuzhiyun const: 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun oneOf: 22*4882a593Smuzhiyun - const: allwinner,sun8i-a83t-de2-clk 23*4882a593Smuzhiyun - const: allwinner,sun8i-h3-de2-clk 24*4882a593Smuzhiyun - const: allwinner,sun8i-v3s-de2-clk 25*4882a593Smuzhiyun - const: allwinner,sun50i-a64-de2-clk 26*4882a593Smuzhiyun - const: allwinner,sun50i-h5-de2-clk 27*4882a593Smuzhiyun - const: allwinner,sun50i-h6-de2-clk 28*4882a593Smuzhiyun - items: 29*4882a593Smuzhiyun - const: allwinner,sun8i-r40-de2-clk 30*4882a593Smuzhiyun - const: allwinner,sun8i-h3-de2-clk 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun reg: 33*4882a593Smuzhiyun maxItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clocks: 36*4882a593Smuzhiyun items: 37*4882a593Smuzhiyun - description: Bus Clock 38*4882a593Smuzhiyun - description: Module Clock 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun clock-names: 41*4882a593Smuzhiyun items: 42*4882a593Smuzhiyun - const: bus 43*4882a593Smuzhiyun - const: mod 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun resets: 46*4882a593Smuzhiyun maxItems: 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunrequired: 49*4882a593Smuzhiyun - "#clock-cells" 50*4882a593Smuzhiyun - "#reset-cells" 51*4882a593Smuzhiyun - compatible 52*4882a593Smuzhiyun - reg 53*4882a593Smuzhiyun - clocks 54*4882a593Smuzhiyun - clock-names 55*4882a593Smuzhiyun - resets 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunadditionalProperties: false 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunexamples: 60*4882a593Smuzhiyun - | 61*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-h3-ccu.h> 62*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-h3-ccu.h> 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun de2_clocks: clock@1000000 { 65*4882a593Smuzhiyun compatible = "allwinner,sun8i-h3-de2-clk"; 66*4882a593Smuzhiyun reg = <0x01000000 0x100000>; 67*4882a593Smuzhiyun clocks = <&ccu CLK_BUS_DE>, 68*4882a593Smuzhiyun <&ccu CLK_DE>; 69*4882a593Smuzhiyun clock-names = "bus", 70*4882a593Smuzhiyun "mod"; 71*4882a593Smuzhiyun resets = <&ccu RST_BUS_DE>; 72*4882a593Smuzhiyun #clock-cells = <1>; 73*4882a593Smuzhiyun #reset-cells = <1>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun... 77