1*4882a593SmuzhiyunDevice State Configuration Registers 2*4882a593Smuzhiyun------------------------------------ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunTI C6X SoCs contain a region of miscellaneous registers which provide various 5*4882a593Smuzhiyunfunction for SoC control or status. Details vary considerably among from SoC 6*4882a593Smuzhiyunto SoC with no two being alike. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunIn general, the Device State Configuration Registers (DSCR) will provide one or 9*4882a593Smuzhiyunmore configuration registers often protected by a lock register where one or 10*4882a593Smuzhiyunmore key values must be written to a lock register in order to unlock the 11*4882a593Smuzhiyunconfiguration register for writes. These configuration register may be used to 12*4882a593Smuzhiyunenable (and disable in some cases) SoC pin drivers, select peripheral clock 13*4882a593Smuzhiyunsources (internal or pin), etc. In some cases, a configuration register is 14*4882a593Smuzhiyunwrite once or the individual bits are write once. In addition to device config, 15*4882a593Smuzhiyunthe DSCR block may provide registers which are used to reset peripherals, 16*4882a593Smuzhiyunprovide device ID information, provide ethernet MAC addresses, as well as other 17*4882a593Smuzhiyunmiscellaneous functions. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunFor device state control (enable/disable), each device control is assigned an 20*4882a593Smuzhiyunid which is used by individual device drivers to control the state as needed. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunRequired properties: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- compatible: must be "ti,c64x+dscr" 25*4882a593Smuzhiyun- reg: register area base and size 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunOptional properties: 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun NOTE: These are optional in that not all SoCs will have all properties. For 30*4882a593Smuzhiyun SoCs which do support a given property, leaving the property out of the 31*4882a593Smuzhiyun device tree will result in reduced functionality or possibly driver 32*4882a593Smuzhiyun failure. 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun- ti,dscr-devstat 35*4882a593Smuzhiyun offset of the devstat register 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun- ti,dscr-silicon-rev 38*4882a593Smuzhiyun offset, start bit, and bitsize of silicon revision field 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun- ti,dscr-rmii-resets 41*4882a593Smuzhiyun offset and bitmask of RMII reset field. May have multiple tuples if more 42*4882a593Smuzhiyun than one ethernet port is available. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun- ti,dscr-locked-regs 45*4882a593Smuzhiyun possibly multiple tuples describing registers which are write protected by 46*4882a593Smuzhiyun a lock register. Each tuple consists of the register offset, lock register 47*4882a593Smuzhiyun offsset, and the key value used to unlock the register. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun- ti,dscr-kick-regs 50*4882a593Smuzhiyun offset and key values of two "kick" registers used to write protect other 51*4882a593Smuzhiyun registers in DSCR. On SoCs using kick registers, the first key must be 52*4882a593Smuzhiyun written to the first kick register and the second key must be written to 53*4882a593Smuzhiyun the second register before other registers in the area are write-enabled. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun- ti,dscr-mac-fuse-regs 56*4882a593Smuzhiyun MAC addresses are contained in two registers. Each element of a MAC address 57*4882a593Smuzhiyun is contained in a single byte. This property has two tuples. Each tuple has 58*4882a593Smuzhiyun a register offset and four cells representing bytes in the register from 59*4882a593Smuzhiyun most significant to least. The value of these four cells is the MAC byte 60*4882a593Smuzhiyun index (1-6) of the byte within the register. A value of 0 means the byte 61*4882a593Smuzhiyun is unused in the MAC address. 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun- ti,dscr-devstate-ctl-regs 64*4882a593Smuzhiyun This property describes the bitfields used to control the state of devices. 65*4882a593Smuzhiyun Each tuple describes a range of identical bitfields used to control one or 66*4882a593Smuzhiyun more devices (one bitfield per device). The layout of each tuple is: 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun start_id num_ids reg enable disable start_bit nbits 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun Where: 71*4882a593Smuzhiyun start_id is device id for the first device control in the range 72*4882a593Smuzhiyun num_ids is the number of device controls in the range 73*4882a593Smuzhiyun reg is the offset of the register holding the control bits 74*4882a593Smuzhiyun enable is the value to enable a device 75*4882a593Smuzhiyun disable is the value to disable a device (0xffffffff if cannot disable) 76*4882a593Smuzhiyun start_bit is the bit number of the first bit in the range 77*4882a593Smuzhiyun nbits is the number of bits per device control 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun- ti,dscr-devstate-stat-regs 80*4882a593Smuzhiyun This property describes the bitfields used to provide device state status 81*4882a593Smuzhiyun for device states controlled by the DSCR. Each tuple describes a range of 82*4882a593Smuzhiyun identical bitfields used to provide status for one or more devices (one 83*4882a593Smuzhiyun bitfield per device). The layout of each tuple is: 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun start_id num_ids reg enable disable start_bit nbits 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun Where: 88*4882a593Smuzhiyun start_id is device id for the first device status in the range 89*4882a593Smuzhiyun num_ids is the number of devices covered by the range 90*4882a593Smuzhiyun reg is the offset of the register holding the status bits 91*4882a593Smuzhiyun enable is the value indicating device is enabled 92*4882a593Smuzhiyun disable is the value indicating device is disabled 93*4882a593Smuzhiyun start_bit is the bit number of the first bit in the range 94*4882a593Smuzhiyun nbits is the number of bits per device status 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun- ti,dscr-privperm 97*4882a593Smuzhiyun Offset and default value for register used to set access privilege for 98*4882a593Smuzhiyun some SoC devices. 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun 101*4882a593SmuzhiyunExample: 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun device-state-config-regs@2a80000 { 104*4882a593Smuzhiyun compatible = "ti,c64x+dscr"; 105*4882a593Smuzhiyun reg = <0x02a80000 0x41000>; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun ti,dscr-devstat = <0>; 108*4882a593Smuzhiyun ti,dscr-silicon-rev = <8 28 0xf>; 109*4882a593Smuzhiyun ti,dscr-rmii-resets = <0x40020 0x00040000>; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>; 112*4882a593Smuzhiyun ti,dscr-devstate-ctl-regs = 113*4882a593Smuzhiyun <0 12 0x40008 1 0 0 2 114*4882a593Smuzhiyun 12 1 0x40008 3 0 30 2 115*4882a593Smuzhiyun 13 2 0x4002c 1 0xffffffff 0 1>; 116*4882a593Smuzhiyun ti,dscr-devstate-stat-regs = 117*4882a593Smuzhiyun <0 10 0x40014 1 0 0 3 118*4882a593Smuzhiyun 10 2 0x40018 1 0 0 3>; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun ti,dscr-mac-fuse-regs = <0x700 1 2 3 4 121*4882a593Smuzhiyun 0x704 5 6 0 0>; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun ti,dscr-privperm = <0x41c 0xaaaaaaaa>; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun ti,dscr-kick-regs = <0x38 0x83E70B13 126*4882a593Smuzhiyun 0x3c 0x95A4F1E0>; 127*4882a593Smuzhiyun }; 128