1*4882a593SmuzhiyunC6X PLL Clock Controllers 2*4882a593Smuzhiyun------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis is a first-cut support for the SoC clock controllers. This is still 5*4882a593Smuzhiyununder development and will probably change as the common device tree 6*4882a593Smuzhiyunclock support is added to the kernel. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- compatible: "ti,c64x+pll" 11*4882a593Smuzhiyun May also have SoC-specific value to support SoC-specific initialization 12*4882a593Smuzhiyun in the driver. One of: 13*4882a593Smuzhiyun "ti,c6455-pll" 14*4882a593Smuzhiyun "ti,c6457-pll" 15*4882a593Smuzhiyun "ti,c6472-pll" 16*4882a593Smuzhiyun "ti,c6474-pll" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- reg: base address and size of register area 19*4882a593Smuzhiyun- clock-frequency: input clock frequency in hz 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunOptional properties: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clock-controller@29a0000 { 33*4882a593Smuzhiyun compatible = "ti,c6472-pll", "ti,c64x+pll"; 34*4882a593Smuzhiyun reg = <0x029a0000 0x200>; 35*4882a593Smuzhiyun clock-frequency = <25000000>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun ti,c64x+pll-bypass-delay = <200>; 38*4882a593Smuzhiyun ti,c64x+pll-reset-delay = <12000>; 39*4882a593Smuzhiyun ti,c64x+pll-lock-delay = <80000>; 40*4882a593Smuzhiyun }; 41