1*4882a593SmuzhiyunBroadcom GISB bus Arbiter controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: 6*4882a593Smuzhiyun "brcm,bcm7278-gisb-arb" for V7 28nm chips 7*4882a593Smuzhiyun "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips 8*4882a593Smuzhiyun "brcm,bcm7435-gisb-arb" for newer 40nm chips 9*4882a593Smuzhiyun "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips 10*4882a593Smuzhiyun "brcm,bcm7038-gisb-arb" for 130nm chips 11*4882a593Smuzhiyun- reg: specifies the base physical address and size of the registers 12*4882a593Smuzhiyun- interrupts: specifies the two interrupts (timeout and TEA) to be used from 13*4882a593Smuzhiyun the parent interrupt controller. A third optional interrupt may be specified 14*4882a593Smuzhiyun for breakpoints. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB 19*4882a593Smuzhiyun masters are valid at the system level 20*4882a593Smuzhiyun- brcm,gisb-arb-master-names: string list of the litteral name of the GISB 21*4882a593Smuzhiyun masters. Should match the number of bits set in brcm,gisb-master-mask and 22*4882a593Smuzhiyun the order in which they appear 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyungisb-arb@f0400000 { 27*4882a593Smuzhiyun compatible = "brcm,gisb-arb"; 28*4882a593Smuzhiyun reg = <0xf0400000 0x800>; 29*4882a593Smuzhiyun interrupts = <0>, <2>; 30*4882a593Smuzhiyun interrupt-parent = <&sun_l2_intc>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun brcm,gisb-arb-master-mask = <0x7>; 33*4882a593Smuzhiyun brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; 34*4882a593Smuzhiyun}; 35