1*4882a593SmuzhiyunDriver for ARM AXI Bus with Broadcom Plugins (bcma) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible : brcm,bus-axi 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- reg : iomem address range of chipcommon core 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe cores on the AXI bus are automatically detected by bcma with the 10*4882a593Smuzhiyunmemory ranges they are using and they get registered afterwards. 11*4882a593SmuzhiyunAutomatic detection of the IRQ number is not working on 12*4882a593SmuzhiyunBCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide 13*4882a593Smuzhiyunthem manually through device tree. Use an interrupt-map to specify the 14*4882a593SmuzhiyunIRQ used by the devices on the bus. The first address is just an index, 15*4882a593Smuzhiyunbecause we do not have any special register. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunThe top-level axi bus may contain children representing attached cores 18*4882a593Smuzhiyun(devices). This is needed since some hardware details can't be auto 19*4882a593Smuzhiyundetected (e.g. IRQ numbers). Also some of the cores may be responsible 20*4882a593Smuzhiyunfor extra things, e.g. ChipCommon providing access to the GPIO chip. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun axi@18000000 { 25*4882a593Smuzhiyun compatible = "brcm,bus-axi"; 26*4882a593Smuzhiyun reg = <0x18000000 0x1000>; 27*4882a593Smuzhiyun ranges = <0x00000000 0x18000000 0x00100000>; 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells = <1>; 30*4882a593Smuzhiyun #interrupt-cells = <1>; 31*4882a593Smuzhiyun interrupt-map-mask = <0x000fffff 0xffff>; 32*4882a593Smuzhiyun interrupt-map = 33*4882a593Smuzhiyun /* Ethernet Controller 0 */ 34*4882a593Smuzhiyun <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Ethernet Controller 1 */ 37*4882a593Smuzhiyun <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* PCIe Controller 0 */ 40*4882a593Smuzhiyun <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 41*4882a593Smuzhiyun <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 42*4882a593Smuzhiyun <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 43*4882a593Smuzhiyun <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 44*4882a593Smuzhiyun <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 45*4882a593Smuzhiyun <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun chipcommon { 48*4882a593Smuzhiyun reg = <0x00000000 0x1000>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun gpio-controller; 51*4882a593Smuzhiyun #gpio-cells = <2>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54