1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Baikal-T1 AXI-bus 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Serge Semin <fancer.lancer@gmail.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all 15*4882a593Smuzhiyun high-speed peripheral IP-cores with RAM controller and with MIPS P5600 16*4882a593Smuzhiyun cores. Traffic arbitration is done by means of DW AXI Interconnect (so 17*4882a593Smuzhiyun called AXI Main Interconnect) routing IO requests from one block to 18*4882a593Smuzhiyun another: from CPU to SoC peripherals and between some SoC peripherals 19*4882a593Smuzhiyun (mostly between peripheral devices and RAM, but also between DMA and 20*4882a593Smuzhiyun some peripherals). In case of any protocol error, device not responding 21*4882a593Smuzhiyun an IRQ is raised and a faulty situation is reported to the AXI EHB 22*4882a593Smuzhiyun (Errors Handler Block) embedded on top of the DW AXI Interconnect and 23*4882a593Smuzhiyun accessible by means of the Baikal-T1 System Controller. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunallOf: 26*4882a593Smuzhiyun - $ref: /schemas/simple-bus.yaml# 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunproperties: 29*4882a593Smuzhiyun compatible: 30*4882a593Smuzhiyun contains: 31*4882a593Smuzhiyun const: baikal,bt1-axi 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reg: 34*4882a593Smuzhiyun minItems: 1 35*4882a593Smuzhiyun items: 36*4882a593Smuzhiyun - description: Synopsys DesignWare AXI Interconnect QoS registers 37*4882a593Smuzhiyun - description: AXI EHB MMIO system controller registers 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun reg-names: 40*4882a593Smuzhiyun minItems: 1 41*4882a593Smuzhiyun items: 42*4882a593Smuzhiyun - const: qos 43*4882a593Smuzhiyun - const: ehb 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun '#interconnect-cells': 46*4882a593Smuzhiyun const: 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun syscon: 49*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/phandle 50*4882a593Smuzhiyun description: Phandle to the Baikal-T1 System Controller DT node 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun interrupts: 53*4882a593Smuzhiyun maxItems: 1 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun clocks: 56*4882a593Smuzhiyun items: 57*4882a593Smuzhiyun - description: Main Interconnect uplink reference clock 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun clock-names: 60*4882a593Smuzhiyun items: 61*4882a593Smuzhiyun - const: aclk 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun resets: 64*4882a593Smuzhiyun items: 65*4882a593Smuzhiyun - description: Main Interconnect reset line 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun reset-names: 68*4882a593Smuzhiyun items: 69*4882a593Smuzhiyun - const: arst 70*4882a593Smuzhiyun 71*4882a593SmuzhiyununevaluatedProperties: false 72*4882a593Smuzhiyun 73*4882a593Smuzhiyunrequired: 74*4882a593Smuzhiyun - compatible 75*4882a593Smuzhiyun - reg 76*4882a593Smuzhiyun - reg-names 77*4882a593Smuzhiyun - syscon 78*4882a593Smuzhiyun - interrupts 79*4882a593Smuzhiyun - clocks 80*4882a593Smuzhiyun - clock-names 81*4882a593Smuzhiyun 82*4882a593Smuzhiyunexamples: 83*4882a593Smuzhiyun - | 84*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/mips-gic.h> 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun bus@1f05a000 { 87*4882a593Smuzhiyun compatible = "baikal,bt1-axi", "simple-bus"; 88*4882a593Smuzhiyun reg = <0x1f05a000 0x1000>, 89*4882a593Smuzhiyun <0x1f04d110 0x8>; 90*4882a593Smuzhiyun reg-names = "qos", "ehb"; 91*4882a593Smuzhiyun #address-cells = <1>; 92*4882a593Smuzhiyun #size-cells = <1>; 93*4882a593Smuzhiyun #interconnect-cells = <1>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun syscon = <&syscon>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun ranges; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun clocks = <&ccu_axi 0>; 102*4882a593Smuzhiyun clock-names = "aclk"; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun resets = <&ccu_axi 0>; 105*4882a593Smuzhiyun reset-names = "arst"; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun... 108