1*4882a593SmuzhiyunTegra SoC SATA AHCI controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties : 4*4882a593Smuzhiyun- compatible : Must be one of: 5*4882a593Smuzhiyun - Tegra124 : "nvidia,tegra124-ahci" 6*4882a593Smuzhiyun - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci" 7*4882a593Smuzhiyun - Tegra210 : "nvidia,tegra210-ahci" 8*4882a593Smuzhiyun- reg : Should contain 2 entries: 9*4882a593Smuzhiyun - AHCI register set (SATA BAR5) 10*4882a593Smuzhiyun - SATA register set 11*4882a593Smuzhiyun- interrupts : Defines the interrupt used by SATA 12*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 13*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 14*4882a593Smuzhiyun- clock-names : Must include the following entries: 15*4882a593Smuzhiyun - sata 16*4882a593Smuzhiyun - sata-oob 17*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 18*4882a593Smuzhiyun See ../reset/reset.txt for details. 19*4882a593Smuzhiyun- reset-names : Must include the following entries: 20*4882a593Smuzhiyun - sata 21*4882a593Smuzhiyun - sata-oob 22*4882a593Smuzhiyun - sata-cold 23*4882a593Smuzhiyun- phys : Must contain an entry for each entry in phy-names. 24*4882a593Smuzhiyun See ../phy/phy-bindings.txt for details. 25*4882a593Smuzhiyun- phy-names : Must include the following entries: 26*4882a593Smuzhiyun - For Tegra124 and Tegra132: 27*4882a593Smuzhiyun - sata-phy : XUSB PADCTL SATA PHY 28*4882a593Smuzhiyun- For Tegra124 and Tegra132: 29*4882a593Smuzhiyun - hvdd-supply : Defines the SATA HVDD regulator 30*4882a593Smuzhiyun - vddio-supply : Defines the SATA VDDIO regulator 31*4882a593Smuzhiyun - avdd-supply : Defines the SATA AVDD regulator 32*4882a593Smuzhiyun - target-5v-supply : Defines the SATA 5V power regulator 33*4882a593Smuzhiyun - target-12v-supply : Defines the SATA 12V power regulator 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunOptional properties: 36*4882a593Smuzhiyun- reg : 37*4882a593Smuzhiyun - AUX register set 38*4882a593Smuzhiyun- clock-names : 39*4882a593Smuzhiyun - cml1 : 40*4882a593Smuzhiyun cml1 clock should be defined here if the PHY driver 41*4882a593Smuzhiyun doesn't manage them. If it does, they should not be. 42*4882a593Smuzhiyun- phy-names : 43*4882a593Smuzhiyun - For T210: 44*4882a593Smuzhiyun - sata-phy 45