1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Faraday Technology FTIDE010 PATA controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Linus Walleij <linus.walleij@linaro.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun This controller is the first Faraday IDE interface block, used in the 14*4882a593Smuzhiyun StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini 15*4882a593Smuzhiyun platform. The controller can do PIO modes 0 through 4, Multi-word DMA 16*4882a593Smuzhiyun (MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun On the Gemini platform, this PATA block is accompanied by a PATA to 19*4882a593Smuzhiyun SATA bridge in order to support SATA. This is why a phandle to that 20*4882a593Smuzhiyun controller is compulsory on that platform. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun The timing properties are unique per-SoC, not per-board. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunproperties: 25*4882a593Smuzhiyun compatible: 26*4882a593Smuzhiyun oneOf: 27*4882a593Smuzhiyun - const: faraday,ftide010 28*4882a593Smuzhiyun - items: 29*4882a593Smuzhiyun - const: cortina,gemini-pata 30*4882a593Smuzhiyun - const: faraday,ftide010 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun reg: 33*4882a593Smuzhiyun maxItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun interrupts: 36*4882a593Smuzhiyun maxItems: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clocks: 39*4882a593Smuzhiyun minItems: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun clock-names: 42*4882a593Smuzhiyun const: PCLK 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun sata: 45*4882a593Smuzhiyun description: 46*4882a593Smuzhiyun phandle to the Gemini PATA to SATA bridge, if available 47*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunrequired: 50*4882a593Smuzhiyun - compatible 51*4882a593Smuzhiyun - reg 52*4882a593Smuzhiyun - interrupts 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunallOf: 55*4882a593Smuzhiyun - $ref: pata-common.yaml# 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun - if: 58*4882a593Smuzhiyun properties: 59*4882a593Smuzhiyun compatible: 60*4882a593Smuzhiyun contains: 61*4882a593Smuzhiyun const: cortina,gemini-pata 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun then: 64*4882a593Smuzhiyun required: 65*4882a593Smuzhiyun - sata 66*4882a593Smuzhiyun 67*4882a593SmuzhiyununevaluatedProperties: false 68*4882a593Smuzhiyun 69*4882a593Smuzhiyunexamples: 70*4882a593Smuzhiyun - | 71*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 72*4882a593Smuzhiyun #include <dt-bindings/clock/cortina,gemini-clock.h> 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun ide@63000000 { 75*4882a593Smuzhiyun compatible = "cortina,gemini-pata", "faraday,ftide010"; 76*4882a593Smuzhiyun reg = <0x63000000 0x100>; 77*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_EDGE_RISING>; 78*4882a593Smuzhiyun clocks = <&gcc GEMINI_CLK_GATE_IDE>; 79*4882a593Smuzhiyun clock-names = "PCLK"; 80*4882a593Smuzhiyun sata = <&sata>; 81*4882a593Smuzhiyun #address-cells = <1>; 82*4882a593Smuzhiyun #size-cells = <0>; 83*4882a593Smuzhiyun ide-port@0 { 84*4882a593Smuzhiyun reg = <0>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun ide-port@1 { 87*4882a593Smuzhiyun reg = <1>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun... 92