1*4882a593Smuzhiyun* Samsung AHCI SATA Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSATA nodes are defined to describe on-chip Serial ATA controllers. 4*4882a593SmuzhiyunEach SATA controller should have its own node. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible : compatible list, contains "samsung,exynos5-sata" 8*4882a593Smuzhiyun- interrupts : <interrupt mapping for SATA IRQ> 9*4882a593Smuzhiyun- reg : <registers mapping> 10*4882a593Smuzhiyun- samsung,sata-freq : <frequency in MHz> 11*4882a593Smuzhiyun- phys : Must contain exactly one entry as specified 12*4882a593Smuzhiyun in phy-bindings.txt 13*4882a593Smuzhiyun- phy-names : Must be "sata-phy" 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 17*4882a593Smuzhiyun- clock-names : Shall be "sata" for the external SATA bus clock, 18*4882a593Smuzhiyun and "sclk_sata" for the internal controller clock. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun sata@122f0000 { 22*4882a593Smuzhiyun compatible = "snps,dwc-ahci"; 23*4882a593Smuzhiyun samsung,sata-freq = <66>; 24*4882a593Smuzhiyun reg = <0x122f0000 0x1ff>; 25*4882a593Smuzhiyun interrupts = <0 115 0>; 26*4882a593Smuzhiyun clocks = <&clock 277>, <&clock 143>; 27*4882a593Smuzhiyun clock-names = "sata", "sclk_sata"; 28*4882a593Smuzhiyun phys = <&sata_phy>; 29*4882a593Smuzhiyun phy-names = "sata-phy"; 30*4882a593Smuzhiyun }; 31