1*4882a593Smuzhiyun* APM X-Gene 6.0 Gb/s SATA host controller nodes 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSATA host controller nodes are defined to describe on-chip Serial ATA 4*4882a593Smuzhiyuncontrollers. Each SATA controller (pair of ports) have its own node. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible : Shall contain: 8*4882a593Smuzhiyun * "apm,xgene-ahci" 9*4882a593Smuzhiyun- reg : First memory resource shall be the AHCI memory 10*4882a593Smuzhiyun resource. 11*4882a593Smuzhiyun Second memory resource shall be the host controller 12*4882a593Smuzhiyun core memory resource. 13*4882a593Smuzhiyun Third memory resource shall be the host controller 14*4882a593Smuzhiyun diagnostic memory resource. 15*4882a593Smuzhiyun 4th memory resource shall be the host controller 16*4882a593Smuzhiyun AXI memory resource. 17*4882a593Smuzhiyun 5th optional memory resource shall be the host 18*4882a593Smuzhiyun controller MUX memory resource if required. 19*4882a593Smuzhiyun- interrupts : Interrupt-specifier for SATA host controller IRQ. 20*4882a593Smuzhiyun- clocks : Reference to the clock entry. 21*4882a593Smuzhiyun- phys : A list of phandles + phy-specifiers, one for each 22*4882a593Smuzhiyun entry in phy-names. 23*4882a593Smuzhiyun- phy-names : Should contain: 24*4882a593Smuzhiyun * "sata-phy" for the SATA 6.0Gbps PHY 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunOptional properties: 27*4882a593Smuzhiyun- dma-coherent : Present if dma operations are coherent 28*4882a593Smuzhiyun- status : Shall be "ok" if enabled or "disabled" if disabled. 29*4882a593Smuzhiyun Default is "ok". 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunExample: 32*4882a593Smuzhiyun sataclk: sataclk { 33*4882a593Smuzhiyun compatible = "fixed-clock"; 34*4882a593Smuzhiyun #clock-cells = <1>; 35*4882a593Smuzhiyun clock-frequency = <100000000>; 36*4882a593Smuzhiyun clock-output-names = "sataclk"; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun phy2: phy@1f22a000 { 40*4882a593Smuzhiyun compatible = "apm,xgene-phy"; 41*4882a593Smuzhiyun reg = <0x0 0x1f22a000 0x0 0x100>; 42*4882a593Smuzhiyun #phy-cells = <1>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun phy3: phy@1f23a000 { 46*4882a593Smuzhiyun compatible = "apm,xgene-phy"; 47*4882a593Smuzhiyun reg = <0x0 0x1f23a000 0x0 0x100>; 48*4882a593Smuzhiyun #phy-cells = <1>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun sata2: sata@1a400000 { 52*4882a593Smuzhiyun compatible = "apm,xgene-ahci"; 53*4882a593Smuzhiyun reg = <0x0 0x1a400000 0x0 0x1000>, 54*4882a593Smuzhiyun <0x0 0x1f220000 0x0 0x1000>, 55*4882a593Smuzhiyun <0x0 0x1f22d000 0x0 0x1000>, 56*4882a593Smuzhiyun <0x0 0x1f22e000 0x0 0x1000>, 57*4882a593Smuzhiyun <0x0 0x1f227000 0x0 0x1000>; 58*4882a593Smuzhiyun interrupts = <0x0 0x87 0x4>; 59*4882a593Smuzhiyun dma-coherent; 60*4882a593Smuzhiyun clocks = <&sataclk 0>; 61*4882a593Smuzhiyun phys = <&phy2 0>; 62*4882a593Smuzhiyun phy-names = "sata-phy"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun sata3: sata@1a800000 { 66*4882a593Smuzhiyun compatible = "apm,xgene-ahci-pcie"; 67*4882a593Smuzhiyun reg = <0x0 0x1a800000 0x0 0x1000>, 68*4882a593Smuzhiyun <0x0 0x1f230000 0x0 0x1000>, 69*4882a593Smuzhiyun <0x0 0x1f23d000 0x0 0x1000>, 70*4882a593Smuzhiyun <0x0 0x1f23e000 0x0 0x1000>, 71*4882a593Smuzhiyun <0x0 0x1f237000 0x0 0x1000>; 72*4882a593Smuzhiyun interrupts = <0x0 0x88 0x4>; 73*4882a593Smuzhiyun dma-coherent; 74*4882a593Smuzhiyun clocks = <&sataclk 0>; 75*4882a593Smuzhiyun phys = <&phy3 0>; 76*4882a593Smuzhiyun phy-names = "sata-phy"; 77*4882a593Smuzhiyun }; 78