1*4882a593Smuzhiyun* AHCI SATA Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSATA nodes are defined to describe on-chip Serial ATA controllers. 4*4882a593SmuzhiyunEach SATA controller should have its own node. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunIt is possible, but not required, to represent each port as a sub-node. 7*4882a593SmuzhiyunIt allows to enable each port independently when dealing with multiple 8*4882a593SmuzhiyunPHYs. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible : compatible string, one of: 12*4882a593Smuzhiyun - "brcm,iproc-ahci" 13*4882a593Smuzhiyun - "hisilicon,hisi-ahci" 14*4882a593Smuzhiyun - "cavium,octeon-7130-ahci" 15*4882a593Smuzhiyun - "ibm,476gtr-ahci" 16*4882a593Smuzhiyun - "marvell,armada-380-ahci" 17*4882a593Smuzhiyun - "marvell,armada-3700-ahci" 18*4882a593Smuzhiyun - "snps,dwc-ahci" 19*4882a593Smuzhiyun - "snps,spear-ahci" 20*4882a593Smuzhiyun - "generic-ahci" 21*4882a593Smuzhiyun- interrupts : <interrupt mapping for SATA IRQ> 22*4882a593Smuzhiyun- reg : <registers mapping> 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunPlease note that when using "generic-ahci" you must also specify a SoC specific 25*4882a593Smuzhiyuncompatible: 26*4882a593Smuzhiyun compatible = "manufacturer,soc-model-ahci", "generic-ahci"; 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunOptional properties: 29*4882a593Smuzhiyun- dma-coherent : Present if dma operations are coherent 30*4882a593Smuzhiyun- clocks : a list of phandle + clock specifier pairs 31*4882a593Smuzhiyun- resets : a list of phandle + reset specifier pairs 32*4882a593Smuzhiyun- target-supply : regulator for SATA target power 33*4882a593Smuzhiyun- phy-supply : regulator for PHY power 34*4882a593Smuzhiyun- phys : reference to the SATA PHY node 35*4882a593Smuzhiyun- phy-names : must be "sata-phy" 36*4882a593Smuzhiyun- ahci-supply : regulator for AHCI controller 37*4882a593Smuzhiyun- ports-implemented : Mask that indicates which ports that the HBA supports 38*4882a593Smuzhiyun are available for software to use. Useful if PORTS_IMPL 39*4882a593Smuzhiyun is not programmed by the BIOS, which is true with 40*4882a593Smuzhiyun some embedded SOC's. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunRequired properties when using sub-nodes: 43*4882a593Smuzhiyun- #address-cells : number of cells to encode an address 44*4882a593Smuzhiyun- #size-cells : number of cells representing the size of an address 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunSub-nodes required properties: 47*4882a593Smuzhiyun- reg : the port number 48*4882a593SmuzhiyunAnd at least one of the following properties: 49*4882a593Smuzhiyun- phys : reference to the SATA PHY node 50*4882a593Smuzhiyun- target-supply : regulator for SATA target power 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunExamples: 53*4882a593Smuzhiyun sata@ffe08000 { 54*4882a593Smuzhiyun compatible = "snps,spear-ahci"; 55*4882a593Smuzhiyun reg = <0xffe08000 0x1000>; 56*4882a593Smuzhiyun interrupts = <115>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunWith sub-nodes: 60*4882a593Smuzhiyun sata@f7e90000 { 61*4882a593Smuzhiyun compatible = "marvell,berlin2q-achi", "generic-ahci"; 62*4882a593Smuzhiyun reg = <0xe90000 0x1000>; 63*4882a593Smuzhiyun interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 64*4882a593Smuzhiyun clocks = <&chip CLKID_SATA>; 65*4882a593Smuzhiyun #address-cells = <1>; 66*4882a593Smuzhiyun #size-cells = <0>; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun sata0: sata-port@0 { 69*4882a593Smuzhiyun reg = <0>; 70*4882a593Smuzhiyun phys = <&sata_phy 0>; 71*4882a593Smuzhiyun target-supply = <®_sata0>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun sata1: sata-port@1 { 75*4882a593Smuzhiyun reg = <1>; 76*4882a593Smuzhiyun phys = <&sata_phy 1>; 77*4882a593Smuzhiyun target-supply = <®_sata1>;; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80