1*4882a593SmuzhiyunMediaTek Serial ATA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci". 5*4882a593Smuzhiyun When using "mediatek,mtk-ahci" compatible strings, you 6*4882a593Smuzhiyun need SoC specific ones in addition, one of: 7*4882a593Smuzhiyun - "mediatek,mt7622-ahci" 8*4882a593Smuzhiyun - reg : Physical base addresses and length of register sets. 9*4882a593Smuzhiyun - interrupts : Interrupt associated with the SATA device. 10*4882a593Smuzhiyun - interrupt-names : Associated name must be: "hostc". 11*4882a593Smuzhiyun - clocks : A list of phandle and clock specifier pairs, one for each 12*4882a593Smuzhiyun entry in clock-names. 13*4882a593Smuzhiyun - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm". 14*4882a593Smuzhiyun - phys : A phandle and PHY specifier pair for the PHY port. 15*4882a593Smuzhiyun - phy-names : Associated name must be: "sata-phy". 16*4882a593Smuzhiyun - ports-implemented : See ./ahci-platform.txt for details. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun - power-domains : A phandle and power domain specifier pair to the power 20*4882a593Smuzhiyun domain which is responsible for collapsing and restoring 21*4882a593Smuzhiyun power to the peripheral. 22*4882a593Smuzhiyun - resets : Must contain an entry for each entry in reset-names. 23*4882a593Smuzhiyun See ../reset/reset.txt for details. 24*4882a593Smuzhiyun - reset-names : Associated names must be: "axi", "sw", "reg". 25*4882a593Smuzhiyun - mediatek,phy-mode : A phandle to the system controller, used to enable 26*4882a593Smuzhiyun SATA function. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun sata: sata@1a200000 { 31*4882a593Smuzhiyun compatible = "mediatek,mt7622-ahci", 32*4882a593Smuzhiyun "mediatek,mtk-ahci"; 33*4882a593Smuzhiyun reg = <0 0x1a200000 0 0x1100>; 34*4882a593Smuzhiyun interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 35*4882a593Smuzhiyun interrupt-names = "hostc"; 36*4882a593Smuzhiyun clocks = <&pciesys CLK_SATA_AHB_EN>, 37*4882a593Smuzhiyun <&pciesys CLK_SATA_AXI_EN>, 38*4882a593Smuzhiyun <&pciesys CLK_SATA_ASIC_EN>, 39*4882a593Smuzhiyun <&pciesys CLK_SATA_RBC_EN>, 40*4882a593Smuzhiyun <&pciesys CLK_SATA_PM_EN>; 41*4882a593Smuzhiyun clock-names = "ahb", "axi", "asic", "rbc", "pm"; 42*4882a593Smuzhiyun phys = <&u3port1 PHY_TYPE_SATA>; 43*4882a593Smuzhiyun phy-names = "sata-phy"; 44*4882a593Smuzhiyun ports-implemented = <0x1>; 45*4882a593Smuzhiyun power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 46*4882a593Smuzhiyun resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, 47*4882a593Smuzhiyun <&pciesys MT7622_SATA_PHY_SW_RST>, 48*4882a593Smuzhiyun <&pciesys MT7622_SATA_PHY_REG_RST>; 49*4882a593Smuzhiyun reset-names = "axi", "sw", "reg"; 50*4882a593Smuzhiyun mediatek,phy-mode = <&pciesys>; 51*4882a593Smuzhiyun }; 52