1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner Memory Bus (MBUS) controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun The MBUS controller drives the MBUS that other devices in the SoC 15*4882a593Smuzhiyun will use to perform DMA. It also has a register interface that 16*4882a593Smuzhiyun allows to monitor and control the bandwidth and priorities for 17*4882a593Smuzhiyun masters on that bus. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun Each device having to perform their DMA through the MBUS must have 20*4882a593Smuzhiyun the interconnects and interconnect-names properties set to the MBUS 21*4882a593Smuzhiyun controller and with "dma-mem" as the interconnect name. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunproperties: 24*4882a593Smuzhiyun "#interconnect-cells": 25*4882a593Smuzhiyun const: 1 26*4882a593Smuzhiyun description: 27*4882a593Smuzhiyun The content of the cell is the MBUS ID. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun compatible: 30*4882a593Smuzhiyun enum: 31*4882a593Smuzhiyun - allwinner,sun5i-a13-mbus 32*4882a593Smuzhiyun - allwinner,sun8i-h3-mbus 33*4882a593Smuzhiyun - allwinner,sun50i-a64-mbus 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun reg: 36*4882a593Smuzhiyun maxItems: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clocks: 39*4882a593Smuzhiyun maxItems: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun dma-ranges: 42*4882a593Smuzhiyun description: 43*4882a593Smuzhiyun See section 2.3.9 of the DeviceTree Specification. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun '#address-cells': true 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun '#size-cells': true 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunrequired: 50*4882a593Smuzhiyun - "#interconnect-cells" 51*4882a593Smuzhiyun - compatible 52*4882a593Smuzhiyun - reg 53*4882a593Smuzhiyun - clocks 54*4882a593Smuzhiyun - dma-ranges 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunadditionalProperties: false 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunexamples: 59*4882a593Smuzhiyun - | 60*4882a593Smuzhiyun #include <dt-bindings/clock/sun5i-ccu.h> 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun mbus: dram-controller@1c01000 { 63*4882a593Smuzhiyun compatible = "allwinner,sun5i-a13-mbus"; 64*4882a593Smuzhiyun reg = <0x01c01000 0x1000>; 65*4882a593Smuzhiyun clocks = <&ccu CLK_MBUS>; 66*4882a593Smuzhiyun #address-cells = <1>; 67*4882a593Smuzhiyun #size-cells = <1>; 68*4882a593Smuzhiyun dma-ranges = <0x00000000 0x40000000 0x20000000>; 69*4882a593Smuzhiyun #interconnect-cells = <1>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun... 73