1*4882a593SmuzhiyunSP810 System Controller 2*4882a593Smuzhiyun----------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun- compatible: standard compatible string for a Primecell peripheral, 7*4882a593Smuzhiyun see Documentation/devicetree/bindings/arm/primecell.yaml 8*4882a593Smuzhiyun for more details 9*4882a593Smuzhiyun should be: "arm,sp810", "arm,primecell" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- reg: standard registers property, physical address and size 12*4882a593Smuzhiyun of the control registers 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- clock-names: from the common clock bindings, for more details see 15*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/clock-bindings.txt; 16*4882a593Smuzhiyun should be: "refclk", "timclk", "apb_pclk" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- clocks: from the common clock bindings, phandle and clock 19*4882a593Smuzhiyun specifier pairs for the entries of clock-names property 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- #clock-cells: from the common clock bindings; 22*4882a593Smuzhiyun should be: <1> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- clock-output-names: from the common clock bindings; 25*4882a593Smuzhiyun should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3" 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- assigned-clocks: from the common clock binding; 28*4882a593Smuzhiyun should be: clock specifier for each output clock of this 29*4882a593Smuzhiyun provider node 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun- assigned-clock-parents: from the common clock binding; 32*4882a593Smuzhiyun should be: phandle of input clock listed in clocks 33*4882a593Smuzhiyun property with the highest frequency 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunExample: 36*4882a593Smuzhiyun v2m_sysctl: sysctl@20000 { 37*4882a593Smuzhiyun compatible = "arm,sp810", "arm,primecell"; 38*4882a593Smuzhiyun reg = <0x020000 0x1000>; 39*4882a593Smuzhiyun clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; 40*4882a593Smuzhiyun clock-names = "refclk", "timclk", "apb_pclk"; 41*4882a593Smuzhiyun #clock-cells = <1>; 42*4882a593Smuzhiyun clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 43*4882a593Smuzhiyun assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; 44*4882a593Smuzhiyun assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun }; 47