xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/omap/prcm.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunOMAP PRCM bindings
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunPower Reset and Clock Manager lists the device clocks and clockdomains under
4*4882a593Smuzhiyuna DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it,
5*4882a593Smuzhiyuneach describing one module and the clock hierarchy under it. see [1] for
6*4882a593Smuzhiyundocumentation about the individual clock/clockdomain nodes.
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/ti/*
9*4882a593Smuzhiyun
10*4882a593SmuzhiyunRequired properties:
11*4882a593Smuzhiyun- compatible:	Must be one of:
12*4882a593Smuzhiyun		"ti,am3-prcm"
13*4882a593Smuzhiyun		"ti,am4-prcm"
14*4882a593Smuzhiyun		"ti,omap2-prcm"
15*4882a593Smuzhiyun		"ti,omap3-prm"
16*4882a593Smuzhiyun		"ti,omap3-cm"
17*4882a593Smuzhiyun		"ti,omap4-cm1"
18*4882a593Smuzhiyun		"ti,omap4-prm"
19*4882a593Smuzhiyun		"ti,omap4-cm2"
20*4882a593Smuzhiyun		"ti,omap4-scrm"
21*4882a593Smuzhiyun		"ti,omap5-prm"
22*4882a593Smuzhiyun		"ti,omap5-cm-core-aon"
23*4882a593Smuzhiyun		"ti,omap5-scrm"
24*4882a593Smuzhiyun		"ti,omap5-cm-core"
25*4882a593Smuzhiyun		"ti,dra7-prm"
26*4882a593Smuzhiyun		"ti,dra7-cm-core-aon"
27*4882a593Smuzhiyun		"ti,dra7-cm-core"
28*4882a593Smuzhiyun		"ti,dm814-prcm"
29*4882a593Smuzhiyun		"ti,dm816-prcm"
30*4882a593Smuzhiyun- reg:		Contains PRCM module register address range
31*4882a593Smuzhiyun		(base address and length)
32*4882a593Smuzhiyun- clocks:	clocks for this module
33*4882a593Smuzhiyun- clockdomains:	clockdomains for this module
34*4882a593Smuzhiyun
35*4882a593SmuzhiyunExample:
36*4882a593Smuzhiyun
37*4882a593Smuzhiyuncm: cm@48004000 {
38*4882a593Smuzhiyun	compatible = "ti,omap3-cm";
39*4882a593Smuzhiyun	reg = <0x48004000 0x4000>;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	cm_clocks: clocks {
42*4882a593Smuzhiyun		#address-cells = <1>;
43*4882a593Smuzhiyun		#size-cells = <0>;
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	cm_clockdomains: clockdomains {
47*4882a593Smuzhiyun	};
48*4882a593Smuzhiyun}
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun&cm_clocks {
51*4882a593Smuzhiyun	omap2_32k_fck: omap_32k_fck {
52*4882a593Smuzhiyun		#clock-cells = <0>;
53*4882a593Smuzhiyun		compatible = "fixed-clock";
54*4882a593Smuzhiyun		clock-frequency = <32768>;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&cm_clockdomains {
59*4882a593Smuzhiyun	core_l3_clkdm: core_l3_clkdm {
60*4882a593Smuzhiyun		compatible = "ti,clockdomain";
61*4882a593Smuzhiyun		clocks = <&sdrc_ick>;
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun};
64