1*4882a593SmuzhiyunOMAP Control Module bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunControl Module contains miscellaneous features under it based on SoC type. 4*4882a593SmuzhiyunPincontrol is one common feature, and it has a specialized support 5*4882a593Smuzhiyundescribed in [1]. Typically some clock nodes are also under control module. 6*4882a593SmuzhiyunSyscon is used to share register level access to drivers external to 7*4882a593Smuzhiyuncontrol module driver itself. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunSee [2] for documentation about clock/clockdomain nodes. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt 12*4882a593Smuzhiyun[2] Documentation/devicetree/bindings/clock/ti/* 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties: 15*4882a593Smuzhiyun- compatible: Must be one of: 16*4882a593Smuzhiyun "ti,am3-scm" 17*4882a593Smuzhiyun "ti,am4-scm" 18*4882a593Smuzhiyun "ti,dm814-scrm" 19*4882a593Smuzhiyun "ti,dm816-scrm" 20*4882a593Smuzhiyun "ti,omap2-scm" 21*4882a593Smuzhiyun "ti,omap3-scm" 22*4882a593Smuzhiyun "ti,omap4-scm-core" 23*4882a593Smuzhiyun "ti,omap4-scm-padconf-core" 24*4882a593Smuzhiyun "ti,omap4-scm-wkup" 25*4882a593Smuzhiyun "ti,omap4-scm-padconf-wkup" 26*4882a593Smuzhiyun "ti,omap5-scm-core" 27*4882a593Smuzhiyun "ti,omap5-scm-padconf-core" 28*4882a593Smuzhiyun "ti,omap5-scm-wkup-pad-conf" 29*4882a593Smuzhiyun "ti,dra7-scm-core" 30*4882a593Smuzhiyun- reg: Contains Control Module register address range 31*4882a593Smuzhiyun (base address and length) 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunOptional properties: 34*4882a593Smuzhiyun- clocks: clocks for this module 35*4882a593Smuzhiyun- clockdomains: clockdomains for this module 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunExamples: 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunscm: scm@2000 { 40*4882a593Smuzhiyun compatible = "ti,omap3-scm", "simple-bus"; 41*4882a593Smuzhiyun reg = <0x2000 0x2000>; 42*4882a593Smuzhiyun #address-cells = <1>; 43*4882a593Smuzhiyun #size-cells = <1>; 44*4882a593Smuzhiyun ranges = <0 0x2000 0x2000>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun omap3_pmx_core: pinmux@30 { 47*4882a593Smuzhiyun compatible = "ti,omap3-padconf", 48*4882a593Smuzhiyun "pinctrl-single"; 49*4882a593Smuzhiyun reg = <0x30 0x230>; 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <0>; 52*4882a593Smuzhiyun #interrupt-cells = <1>; 53*4882a593Smuzhiyun interrupt-controller; 54*4882a593Smuzhiyun pinctrl-single,register-width = <16>; 55*4882a593Smuzhiyun pinctrl-single,function-mask = <0xff1f>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun scm_conf: scm_conf@270 { 59*4882a593Smuzhiyun compatible = "syscon"; 60*4882a593Smuzhiyun reg = <0x270 0x330>; 61*4882a593Smuzhiyun #address-cells = <1>; 62*4882a593Smuzhiyun #size-cells = <1>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun scm_clocks: clocks { 65*4882a593Smuzhiyun #address-cells = <1>; 66*4882a593Smuzhiyun #size-cells = <0>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun scm_clockdomains: clockdomains { 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun} 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&scm_clocks { 75*4882a593Smuzhiyun mcbsp5_mux_fck: mcbsp5_mux_fck { 76*4882a593Smuzhiyun #clock-cells = <0>; 77*4882a593Smuzhiyun compatible = "ti,composite-mux-clock"; 78*4882a593Smuzhiyun clocks = <&core_96m_fck>, <&mcbsp_clks>; 79*4882a593Smuzhiyun ti,bit-shift = <4>; 80*4882a593Smuzhiyun reg = <0x02d8>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun}; 83