1*4882a593SmuzhiyunSome socs have a large number of interrupts requests to service 2*4882a593Smuzhiyunthe needs of its many peripherals and subsystems. All of the 3*4882a593Smuzhiyuninterrupt lines from the subsystems are not needed at the same 4*4882a593Smuzhiyuntime, so they have to be muxed to the irq-controller appropriately. 5*4882a593SmuzhiyunIn such places a interrupt controllers are preceded by an CROSSBAR 6*4882a593Smuzhiyunthat provides flexibility in muxing the device requests to the controller 7*4882a593Smuzhiyuninputs. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible : Should be "ti,irq-crossbar" 11*4882a593Smuzhiyun- reg: Base address and the size of the crossbar registers. 12*4882a593Smuzhiyun- interrupt-controller: indicates that this block is an interrupt controller. 13*4882a593Smuzhiyun- ti,max-irqs: Total number of irqs available at the parent interrupt controller. 14*4882a593Smuzhiyun- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. 15*4882a593Smuzhiyun- ti,reg-size: Size of a individual register in bytes. Every individual 16*4882a593Smuzhiyun register is assumed to be of same size. Valid sizes are 1, 2, 4. 17*4882a593Smuzhiyun- ti,irqs-reserved: List of the reserved irq lines that are not muxed using 18*4882a593Smuzhiyun crossbar. These interrupt lines are reserved in the soc, 19*4882a593Smuzhiyun so crossbar bar driver should not consider them as free 20*4882a593Smuzhiyun lines. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunOptional properties: 23*4882a593Smuzhiyun- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for 24*4882a593Smuzhiyun SOC-specific hard-wiring of those irqs which unexpectedly bypasses the 25*4882a593Smuzhiyun crossbar. These irqs have a crossbar register, but still cannot be used. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- ti,irqs-safe-map: integer which maps to a safe configuration to use 28*4882a593Smuzhiyun when the interrupt controller irq is unused (when not provided, default is 0) 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExamples: 31*4882a593Smuzhiyun crossbar_mpu: crossbar@4a002a48 { 32*4882a593Smuzhiyun compatible = "ti,irq-crossbar"; 33*4882a593Smuzhiyun reg = <0x4a002a48 0x130>; 34*4882a593Smuzhiyun ti,max-irqs = <160>; 35*4882a593Smuzhiyun ti,max-crossbar-sources = <400>; 36*4882a593Smuzhiyun ti,reg-size = <2>; 37*4882a593Smuzhiyun ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 38*4882a593Smuzhiyun ti,irqs-skip = <10 133 139 140>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunConsumer: 42*4882a593Smuzhiyun======== 43*4882a593SmuzhiyunSee Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and 44*4882a593SmuzhiyunDocumentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for 45*4882a593Smuzhiyunfurther details. 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunAn interrupt consumer on an SoC using crossbar will use: 48*4882a593Smuzhiyun interrupts = <GIC_SPI request_number interrupt_level> 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunExample: 51*4882a593Smuzhiyun device_x@4a023000 { 52*4882a593Smuzhiyun /* Crossbar 8 used */ 53*4882a593Smuzhiyun interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 54*4882a593Smuzhiyun ... 55*4882a593Smuzhiyun }; 56