1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright 2020 thingy.jp. 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#" 6*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: MStar/SigmaStar Armv7 SoC l3bridge 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Daniel Palmer <daniel@thingy.jp> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface 15*4882a593Smuzhiyun between the CPU and memory. This means that before DMA capable 16*4882a593Smuzhiyun devices are allowed to run the pipeline must be flushed to ensure 17*4882a593Smuzhiyun everything is in memory. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun The l3bridge region contains registers that allow such a flush 20*4882a593Smuzhiyun to be triggered. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun This node is used by the platform code to find where the registers 23*4882a593Smuzhiyun are and install a barrier that triggers the required pipeline flush. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunproperties: 26*4882a593Smuzhiyun compatible: 27*4882a593Smuzhiyun items: 28*4882a593Smuzhiyun - const: mstar,l3bridge 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun reg: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyunrequired: 34*4882a593Smuzhiyun - compatible 35*4882a593Smuzhiyun - reg 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunadditionalProperties: false 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunexamples: 40*4882a593Smuzhiyun - | 41*4882a593Smuzhiyun l3bridge: l3bridge@1f204400 { 42*4882a593Smuzhiyun compatible = "mstar,l3bridge"; 43*4882a593Smuzhiyun reg = <0x1f204400 0x200>; 44*4882a593Smuzhiyun }; 45