1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Last Level Cache Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Rishabh Bhatnagar <rishabhb@codeaurora.org> 11*4882a593Smuzhiyun - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, 15*4882a593Smuzhiyun that can be shared by multiple clients. Clients here are different cores in the 16*4882a593Smuzhiyun SoC, the idea is to minimize the local caches at the clients and migrate to 17*4882a593Smuzhiyun common pool of memory. Cache memory is divided into partitions called slices 18*4882a593Smuzhiyun which are assigned to clients. Clients can query the slice details, activate 19*4882a593Smuzhiyun and deactivate them. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunproperties: 22*4882a593Smuzhiyun compatible: 23*4882a593Smuzhiyun enum: 24*4882a593Smuzhiyun - qcom,sc7180-llcc 25*4882a593Smuzhiyun - qcom,sdm845-llcc 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - description: LLCC base register region 30*4882a593Smuzhiyun - description: LLCC broadcast base register region 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun reg-names: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - const: llcc_base 35*4882a593Smuzhiyun - const: llcc_broadcast_base 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun interrupts: 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunrequired: 41*4882a593Smuzhiyun - compatible 42*4882a593Smuzhiyun - reg 43*4882a593Smuzhiyun - reg-names 44*4882a593Smuzhiyun - interrupts 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunadditionalProperties: false 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunexamples: 49*4882a593Smuzhiyun - | 50*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun system-cache-controller@1100000 { 53*4882a593Smuzhiyun compatible = "qcom,sdm845-llcc"; 54*4882a593Smuzhiyun reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; 55*4882a593Smuzhiyun reg-names = "llcc_base", "llcc_broadcast_base"; 56*4882a593Smuzhiyun interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 57*4882a593Smuzhiyun }; 58