1*4882a593SmuzhiyunKrait Processor Sub-system (KPSS) Global Clock Controller (GCC) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPROPERTIES 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: 6*4882a593Smuzhiyun Usage: required 7*4882a593Smuzhiyun Value type: <string> 8*4882a593Smuzhiyun Definition: should be one of the following. The generic compatible 9*4882a593Smuzhiyun "qcom,kpss-gcc" should also be included. 10*4882a593Smuzhiyun "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" 11*4882a593Smuzhiyun "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" 12*4882a593Smuzhiyun "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" 13*4882a593Smuzhiyun "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- reg: 16*4882a593Smuzhiyun Usage: required 17*4882a593Smuzhiyun Value type: <prop-encoded-array> 18*4882a593Smuzhiyun Definition: base address and size of the register region 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- clocks: 21*4882a593Smuzhiyun Usage: required 22*4882a593Smuzhiyun Value type: <prop-encoded-array> 23*4882a593Smuzhiyun Definition: reference to the pll parents. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun- clock-names: 26*4882a593Smuzhiyun Usage: required 27*4882a593Smuzhiyun Value type: <stringlist> 28*4882a593Smuzhiyun Definition: must be "pll8_vote", "pxo". 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun- clock-output-names: 31*4882a593Smuzhiyun Usage: required 32*4882a593Smuzhiyun Value type: <string> 33*4882a593Smuzhiyun Definition: Name of the output clock. Typically acpu_l2_aux indicating 34*4882a593Smuzhiyun an L2 cache auxiliary clock. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunExample: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun l2cc: clock-controller@2011000 { 39*4882a593Smuzhiyun compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; 40*4882a593Smuzhiyun reg = <0x2011000 0x1000>; 41*4882a593Smuzhiyun clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; 42*4882a593Smuzhiyun clock-names = "pll8_vote", "pxo"; 43*4882a593Smuzhiyun clock-output-names = "acpu_l2_aux"; 44*4882a593Smuzhiyun }; 45