1*4882a593SmuzhiyunKrait Processor Sub-system (KPSS) Application Clock Controller (ACC) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe KPSS ACC provides clock, power domain, and reset control to a Krait CPU. 4*4882a593SmuzhiyunThere is one ACC register region per CPU within the KPSS remapped region as 5*4882a593Smuzhiyunwell as an alias register region that remaps accesses to the ACC associated 6*4882a593Smuzhiyunwith the CPU accessing the region. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunPROPERTIES 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- compatible: 11*4882a593Smuzhiyun Usage: required 12*4882a593Smuzhiyun Value type: <string> 13*4882a593Smuzhiyun Definition: should be one of: 14*4882a593Smuzhiyun "qcom,kpss-acc-v1" 15*4882a593Smuzhiyun "qcom,kpss-acc-v2" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- reg: 18*4882a593Smuzhiyun Usage: required 19*4882a593Smuzhiyun Value type: <prop-encoded-array> 20*4882a593Smuzhiyun Definition: the first element specifies the base address and size of 21*4882a593Smuzhiyun the register region. An optional second element specifies 22*4882a593Smuzhiyun the base address and size of the alias register region. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- clocks: 25*4882a593Smuzhiyun Usage: required 26*4882a593Smuzhiyun Value type: <prop-encoded-array> 27*4882a593Smuzhiyun Definition: reference to the pll parents. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- clock-names: 30*4882a593Smuzhiyun Usage: required 31*4882a593Smuzhiyun Value type: <stringlist> 32*4882a593Smuzhiyun Definition: must be "pll8_vote", "pxo". 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun- clock-output-names: 35*4882a593Smuzhiyun Usage: optional 36*4882a593Smuzhiyun Value type: <string> 37*4882a593Smuzhiyun Definition: Name of the output clock. Typically acpuX_aux where X is a 38*4882a593Smuzhiyun CPU number starting at 0. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun clock-controller@2088000 { 43*4882a593Smuzhiyun compatible = "qcom,kpss-acc-v2"; 44*4882a593Smuzhiyun reg = <0x02088000 0x1000>, 45*4882a593Smuzhiyun <0x02008000 0x1000>; 46*4882a593Smuzhiyun clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; 47*4882a593Smuzhiyun clock-names = "pll8_vote", "pxo"; 48*4882a593Smuzhiyun clock-output-names = "acpu0_aux"; 49*4882a593Smuzhiyun }; 50