1*4882a593SmuzhiyunMediatek mmsys controller 2*4882a593Smuzhiyun============================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Mediatek mmsys system controller provides clock control, routing control, 5*4882a593Smuzhiyunand miscellaneous control in mmsys partition. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: Should be one of: 10*4882a593Smuzhiyun - "mediatek,mt2701-mmsys", "syscon" 11*4882a593Smuzhiyun - "mediatek,mt2712-mmsys", "syscon" 12*4882a593Smuzhiyun - "mediatek,mt6765-mmsys", "syscon" 13*4882a593Smuzhiyun - "mediatek,mt6779-mmsys", "syscon" 14*4882a593Smuzhiyun - "mediatek,mt6797-mmsys", "syscon" 15*4882a593Smuzhiyun - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" 16*4882a593Smuzhiyun - "mediatek,mt8173-mmsys", "syscon" 17*4882a593Smuzhiyun - "mediatek,mt8183-mmsys", "syscon" 18*4882a593Smuzhiyun- #clock-cells: Must be 1 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunFor the clock control, the mmsys controller uses the common clk binding from 21*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 22*4882a593SmuzhiyunThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunmmsys: syscon@14000000 { 27*4882a593Smuzhiyun compatible = "mediatek,mt8173-mmsys", "syscon"; 28*4882a593Smuzhiyun reg = <0 0x14000000 0 0x1000>; 29*4882a593Smuzhiyun #clock-cells = <1>; 30*4882a593Smuzhiyun}; 31