1*4882a593SmuzhiyunMediatek apmixedsys controller 2*4882a593Smuzhiyun============================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Mediatek apmixedsys controller provides the PLLs to the system. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: Should be one of: 9*4882a593Smuzhiyun - "mediatek,mt2701-apmixedsys" 10*4882a593Smuzhiyun - "mediatek,mt2712-apmixedsys", "syscon" 11*4882a593Smuzhiyun - "mediatek,mt6765-apmixedsys", "syscon" 12*4882a593Smuzhiyun - "mediatek,mt6779-apmixedsys", "syscon" 13*4882a593Smuzhiyun - "mediatek,mt6797-apmixedsys" 14*4882a593Smuzhiyun - "mediatek,mt7622-apmixedsys" 15*4882a593Smuzhiyun - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" 16*4882a593Smuzhiyun - "mediatek,mt7629-apmixedsys" 17*4882a593Smuzhiyun - "mediatek,mt8135-apmixedsys" 18*4882a593Smuzhiyun - "mediatek,mt8167-apmixedsys", "syscon" 19*4882a593Smuzhiyun - "mediatek,mt8173-apmixedsys" 20*4882a593Smuzhiyun - "mediatek,mt8183-apmixedsys", "syscon" 21*4882a593Smuzhiyun - "mediatek,mt8516-apmixedsys" 22*4882a593Smuzhiyun- #clock-cells: Must be 1 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunThe apmixedsys controller uses the common clk binding from 25*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 26*4882a593SmuzhiyunThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunapmixedsys: clock-controller@10209000 { 31*4882a593Smuzhiyun compatible = "mediatek,mt8173-apmixedsys"; 32*4882a593Smuzhiyun reg = <0 0x10209000 0 0x1000>; 33*4882a593Smuzhiyun #clock-cells = <1>; 34*4882a593Smuzhiyun}; 35