1*4882a593SmuzhiyunMediatek vencsys controller 2*4882a593Smuzhiyun============================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Mediatek vencsys controller provides various clocks to the system. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: Should be one of: 9*4882a593Smuzhiyun - "mediatek,mt2712-vencsys", "syscon" 10*4882a593Smuzhiyun - "mediatek,mt6779-vencsys", "syscon" 11*4882a593Smuzhiyun - "mediatek,mt6797-vencsys", "syscon" 12*4882a593Smuzhiyun - "mediatek,mt8173-vencsys", "syscon" 13*4882a593Smuzhiyun - "mediatek,mt8183-vencsys", "syscon" 14*4882a593Smuzhiyun- #clock-cells: Must be 1 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunThe vencsys controller uses the common clk binding from 17*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 18*4882a593SmuzhiyunThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunvencsys: clock-controller@18000000 { 23*4882a593Smuzhiyun compatible = "mediatek,mt8173-vencsys", "syscon"; 24*4882a593Smuzhiyun reg = <0 0x18000000 0 0x1000>; 25*4882a593Smuzhiyun #clock-cells = <1>; 26*4882a593Smuzhiyun}; 27