xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunMediaTek PCIESYS controller
2*4882a593Smuzhiyun============================
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunThe MediaTek PCIESYS controller provides various clocks to the system.
5*4882a593Smuzhiyun
6*4882a593SmuzhiyunRequired Properties:
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun- compatible: Should be:
9*4882a593Smuzhiyun	- "mediatek,mt7622-pciesys", "syscon"
10*4882a593Smuzhiyun	- "mediatek,mt7629-pciesys", "syscon"
11*4882a593Smuzhiyun- #clock-cells: Must be 1
12*4882a593Smuzhiyun- #reset-cells: Must be 1
13*4882a593Smuzhiyun
14*4882a593SmuzhiyunThe PCIESYS controller uses the common clk binding from
15*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt
16*4882a593SmuzhiyunThe available clocks are defined in dt-bindings/clock/mt*-clk.h.
17*4882a593Smuzhiyun
18*4882a593SmuzhiyunExample:
19*4882a593Smuzhiyun
20*4882a593Smuzhiyunpciesys: pciesys@1a100800 {
21*4882a593Smuzhiyun	compatible = "mediatek,mt7622-pciesys", "syscon";
22*4882a593Smuzhiyun	reg = <0 0x1a100800 0 0x1000>;
23*4882a593Smuzhiyun	#clock-cells = <1>;
24*4882a593Smuzhiyun	#reset-cells = <1>;
25*4882a593Smuzhiyun};
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