1*4882a593SmuzhiyunMediatek mipi0a (mipi_rx_ana_csi0a) controller 2*4882a593Smuzhiyun============================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Mediatek mipi0a controller provides various clocks 5*4882a593Smuzhiyunto the system. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: Should be one of: 10*4882a593Smuzhiyun - "mediatek,mt6765-mipi0a", "syscon" 11*4882a593Smuzhiyun- #clock-cells: Must be 1 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunThe mipi0a controller uses the common clk binding from 14*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 15*4882a593SmuzhiyunThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunThe mipi0a controller also uses the common power domain from 18*4882a593SmuzhiyunDocumentation/devicetree/bindings/soc/mediatek/scpsys.txt 19*4882a593SmuzhiyunThe available power doamins are defined in dt-bindings/power/mt*-power.h. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunmipi0a: clock-controller@11c10000 { 24*4882a593Smuzhiyun compatible = "mediatek,mt6765-mipi0a", "syscon"; 25*4882a593Smuzhiyun reg = <0 0x11c10000 0 0x1000>; 26*4882a593Smuzhiyun power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>; 27*4882a593Smuzhiyun #clock-cells = <1>; 28*4882a593Smuzhiyun}; 29