1*4882a593SmuzhiyunMediatek imgsys controller 2*4882a593Smuzhiyun============================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Mediatek imgsys controller provides various clocks to the system. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: Should be one of: 9*4882a593Smuzhiyun - "mediatek,mt2701-imgsys", "syscon" 10*4882a593Smuzhiyun - "mediatek,mt2712-imgsys", "syscon" 11*4882a593Smuzhiyun - "mediatek,mt6765-imgsys", "syscon" 12*4882a593Smuzhiyun - "mediatek,mt6779-imgsys", "syscon" 13*4882a593Smuzhiyun - "mediatek,mt6797-imgsys", "syscon" 14*4882a593Smuzhiyun - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" 15*4882a593Smuzhiyun - "mediatek,mt8167-imgsys", "syscon" 16*4882a593Smuzhiyun - "mediatek,mt8173-imgsys", "syscon" 17*4882a593Smuzhiyun - "mediatek,mt8183-imgsys", "syscon" 18*4882a593Smuzhiyun- #clock-cells: Must be 1 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThe imgsys controller uses the common clk binding from 21*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 22*4882a593SmuzhiyunThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunimgsys: clock-controller@15000000 { 27*4882a593Smuzhiyun compatible = "mediatek,mt8173-imgsys", "syscon"; 28*4882a593Smuzhiyun reg = <0 0x15000000 0 0x1000>; 29*4882a593Smuzhiyun #clock-cells = <1>; 30*4882a593Smuzhiyun}; 31