1*4882a593SmuzhiyunMediaTek g3dsys controller 2*4882a593Smuzhiyun============================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe MediaTek g3dsys controller provides various clocks and reset controller to 5*4882a593Smuzhiyunthe GPU. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: Should be: 10*4882a593Smuzhiyun - "mediatek,mt2701-g3dsys", "syscon": 11*4882a593Smuzhiyun for MT2701 SoC 12*4882a593Smuzhiyun - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon": 13*4882a593Smuzhiyun for MT7623 SoC 14*4882a593Smuzhiyun- #clock-cells: Must be 1 15*4882a593Smuzhiyun- #reset-cells: Must be 1 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunThe g3dsys controller uses the common clk binding from 18*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 19*4882a593SmuzhiyunThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyung3dsys: clock-controller@13000000 { 24*4882a593Smuzhiyun compatible = "mediatek,mt7623-g3dsys", 25*4882a593Smuzhiyun "mediatek,mt2701-g3dsys", 26*4882a593Smuzhiyun "syscon"; 27*4882a593Smuzhiyun reg = <0 0x13000000 0 0x200>; 28*4882a593Smuzhiyun #clock-cells = <1>; 29*4882a593Smuzhiyun #reset-cells = <1>; 30*4882a593Smuzhiyun}; 31