1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2*4882a593Smuzhiyun# 3*4882a593Smuzhiyun# (C) COPYRIGHT 2013-2022 ARM Limited. All rights reserved. 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun# This program is free software and is provided to you under the terms of the 6*4882a593Smuzhiyun# GNU General Public License version 2 as published by the Free Software 7*4882a593Smuzhiyun# Foundation, and any use by you of this program is subject to the terms 8*4882a593Smuzhiyun# of such GNU license. 9*4882a593Smuzhiyun# 10*4882a593Smuzhiyun# This program is distributed in the hope that it will be useful, 11*4882a593Smuzhiyun# but WITHOUT ANY WARRANTY; without even the implied warranty of 12*4882a593Smuzhiyun# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*4882a593Smuzhiyun# GNU General Public License for more details. 14*4882a593Smuzhiyun# 15*4882a593Smuzhiyun# You should have received a copy of the GNU General Public License 16*4882a593Smuzhiyun# along with this program; if not, you can access it online at 17*4882a593Smuzhiyun# http://www.gnu.org/licenses/gpl-2.0.html. 18*4882a593Smuzhiyun# 19*4882a593Smuzhiyun# 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun* ARM Mali Midgard / Bifrost devices 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunRequired properties: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- compatible : Should be mali<chip>, replacing digits with x from the back, 27*4882a593Smuzhiyununtil malit<Major>xx, and it must end with one of: "arm,malit6xx" or 28*4882a593Smuzhiyun"arm,mali-midgard" or "arm,mali-bifrost" 29*4882a593Smuzhiyun- reg : Physical base address of the device and length of the register area. 30*4882a593Smuzhiyun- interrupts : Contains the three IRQ lines required by T-6xx devices 31*4882a593Smuzhiyun- interrupt-names : Contains the names of IRQ resources in the order they were 32*4882a593Smuzhiyunprovided in the interrupts property. Must contain: "JOB, "MMU", "GPU". 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunOptional: 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun- clocks : One or more pairs of phandle to clock and clock specifier 37*4882a593Smuzhiyun for the Mali device. The order is important: the first clock 38*4882a593Smuzhiyun shall correspond to the "clk_mali" source, while the second clock 39*4882a593Smuzhiyun (that is optional) shall correspond to the "shadercores" source. 40*4882a593Smuzhiyun- clock-names : Shall be set to: "clk_mali", "shadercores". 41*4882a593Smuzhiyun- mali-supply : Phandle to the top level regulator for the Mali device. 42*4882a593Smuzhiyun Refer to 43*4882a593SmuzhiyunDocumentation/devicetree/bindings/regulator/regulator.txt for details. 44*4882a593Smuzhiyun- mem-supply : Phandle to memory regulator for the Mali device. This is optional. 45*4882a593Smuzhiyun- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/mali-opp.txt 46*4882a593Smuzhiyunfor details. 47*4882a593Smuzhiyun- quirks_gpu : Used to write to the JM_CONFIG or CSF_CONFIG register. 48*4882a593Smuzhiyun Should be used with care. Options passed here are used to override 49*4882a593Smuzhiyun certain default behavior. Note: This will override 'idvs-group-size' 50*4882a593Smuzhiyun field in devicetree and module param 'corestack_driver_control', 51*4882a593Smuzhiyun therefore if 'quirks_gpu' is used then 'idvs-group-size' and 52*4882a593Smuzhiyun 'corestack_driver_control' value should be incorporated into 'quirks_gpu'. 53*4882a593Smuzhiyun- quirks_sc : Used to write to the SHADER_CONFIG register. 54*4882a593Smuzhiyun Should be used with care. Options passed here are used to override 55*4882a593Smuzhiyun certain default behavior. 56*4882a593Smuzhiyun- quirks_tiler : Used to write to the TILER_CONFIG register. 57*4882a593Smuzhiyun Should be used with care. Options passed here are used to 58*4882a593Smuzhiyun disable or override certain default behavior. 59*4882a593Smuzhiyun- quirks_mmu : Used to write to the L2_CONFIG register. 60*4882a593Smuzhiyun Should be used with care. Options passed here are used to 61*4882a593Smuzhiyun disable or override certain default behavior. 62*4882a593Smuzhiyun- power_model : Sets the power model parameters. Defined power models include: 63*4882a593Smuzhiyun "mali-simple-power-model", "mali-g51-power-model", "mali-g52-power-model", 64*4882a593Smuzhiyun "mali-g52_r1-power-model", "mali-g71-power-model", "mali-g72-power-model", 65*4882a593Smuzhiyun "mali-g76-power-model", "mali-g77-power-model", "mali-tnax-power-model", 66*4882a593Smuzhiyun "mali-tbex-power-model" and "mali-tbax-power-model". 67*4882a593Smuzhiyun - mali-simple-power-model: this model derives the GPU power usage based 68*4882a593Smuzhiyun on the GPU voltage scaled by the system temperature. Note: it was 69*4882a593Smuzhiyun designed for the Juno platform, and may not be suitable for others. 70*4882a593Smuzhiyun - compatible: Should be "arm,mali-simple-power-model" 71*4882a593Smuzhiyun - dynamic-coefficient: Coefficient, in pW/(Hz V^2), which is 72*4882a593Smuzhiyun multiplied by v^2*f to calculate the dynamic power consumption. 73*4882a593Smuzhiyun - static-coefficient: Coefficient, in uW/V^3, which is 74*4882a593Smuzhiyun multiplied by v^3 to calculate the static power consumption. 75*4882a593Smuzhiyun - ts: An array containing coefficients for the temperature 76*4882a593Smuzhiyun scaling factor. This is used to scale the static power by a 77*4882a593Smuzhiyun factor of tsf/1000000, 78*4882a593Smuzhiyun where tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0], 79*4882a593Smuzhiyun and T = temperature in degrees. 80*4882a593Smuzhiyun - thermal-zone: A string identifying the thermal zone used for 81*4882a593Smuzhiyun the GPU 82*4882a593Smuzhiyun - temp-poll-interval-ms: the interval at which the system 83*4882a593Smuzhiyun temperature is polled 84*4882a593Smuzhiyun - mali-g*-power-model(s): unless being stated otherwise, these models derive 85*4882a593Smuzhiyun the GPU power usage based on performance counters, so they are more 86*4882a593Smuzhiyun accurate. 87*4882a593Smuzhiyun - compatible: Should be, as examples, "arm,mali-g51-power-model" / 88*4882a593Smuzhiyun "arm,mali-g72-power-model". 89*4882a593Smuzhiyun - scale: the dynamic power calculated by the power model is 90*4882a593Smuzhiyun multiplied by a factor of 'scale'. This value should be 91*4882a593Smuzhiyun chosen to match a particular implementation. 92*4882a593Smuzhiyun - min_sample_cycles: Fall back to the simple power model if the 93*4882a593Smuzhiyun number of GPU cycles for a given counter dump is less than 94*4882a593Smuzhiyun 'min_sample_cycles'. The default value of this should suffice. 95*4882a593Smuzhiyun * Note: when IPA is used, two separate power models (simple and counter-based) 96*4882a593Smuzhiyun are used at different points so care should be taken to configure 97*4882a593Smuzhiyun both power models in the device tree (specifically dynamic-coefficient, 98*4882a593Smuzhiyun static-coefficient and scale) to best match the platform. 99*4882a593Smuzhiyun- power_policy : Sets the GPU power policy at probe time. Available options are 100*4882a593Smuzhiyun "coarse_demand" and "always_on". If not set, then "coarse_demand" is used. 101*4882a593Smuzhiyun- system-coherency : Sets the coherency protocol to be used for coherent 102*4882a593Smuzhiyun accesses made from the GPU. 103*4882a593Smuzhiyun If not set then no coherency is used. 104*4882a593Smuzhiyun - 0 : ACE-Lite 105*4882a593Smuzhiyun - 1 : ACE 106*4882a593Smuzhiyun - 31 : No coherency 107*4882a593Smuzhiyun- ipa-model : Sets the IPA model to be used for power management. GPU probe will fail if the 108*4882a593Smuzhiyun model is not found in the registered models list. If no model is specified here, 109*4882a593Smuzhiyun a gpu-id based model is picked if available, otherwise the default model is used. 110*4882a593Smuzhiyun - mali-simple-power-model: Default model used on mali 111*4882a593Smuzhiyun- idvs-group-size : Override the IDVS group size value. Tasks are sent to 112*4882a593Smuzhiyun cores in groups of N + 1, so i.e. 0xF means 16 tasks. 113*4882a593Smuzhiyun Valid values are between 0 to 0x3F (including). 114*4882a593Smuzhiyun- l2-size : Override L2 cache size on GPU that supports it 115*4882a593Smuzhiyun- l2-hash : Override L2 hash function on GPU that supports it 116*4882a593Smuzhiyun- l2-hash-values : Override L2 hash function using provided hash values, on GPUs that supports it. 117*4882a593Smuzhiyun It is mutually exclusive with 'l2-hash'. Only one or the other must be 118*4882a593Smuzhiyun used in a supported GPU. 119*4882a593Smuzhiyun- arbiter_if : Phandle to the arbif platform device, used to provide KBASE with an interface 120*4882a593Smuzhiyun to the Arbiter. This is required when using arbitration; setting to a non-NULL 121*4882a593Smuzhiyun value will enable arbitration. 122*4882a593Smuzhiyun If arbitration is in use, then there should be no external GPU control. 123*4882a593Smuzhiyun When arbiter_if is in use then the following must not be: 124*4882a593Smuzhiyun - power_model (no IPA allowed with arbitration) 125*4882a593Smuzhiyun - #cooling-cells 126*4882a593Smuzhiyun - operating-points-v2 (no dvfs in kbase with arbitration) 127*4882a593Smuzhiyun - system-coherency with a value of 1 (no full coherency with arbitration) 128*4882a593Smuzhiyun- int_id_override: list of <ID Setting[7:0]> tuples defining the IDs needed to be 129*4882a593Smuzhiyun set and the setting coresponding to the SYSC_ALLOC register. 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun 132*4882a593SmuzhiyunExample for a Mali GPU with 1 clock and 1 regulator: 133*4882a593Smuzhiyun 134*4882a593Smuzhiyungpu@0xfc010000 { 135*4882a593Smuzhiyun compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 136*4882a593Smuzhiyun reg = <0xfc010000 0x4000>; 137*4882a593Smuzhiyun interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 138*4882a593Smuzhiyun interrupt-names = "JOB", "MMU", "GPU"; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun clocks = <&pclk_mali>; 141*4882a593Smuzhiyun clock-names = "clk_mali"; 142*4882a593Smuzhiyun mali-supply = <&vdd_mali>; 143*4882a593Smuzhiyun operating-points-v2 = <&gpu_opp_table>; 144*4882a593Smuzhiyun power_model@0 { 145*4882a593Smuzhiyun compatible = "arm,mali-simple-power-model"; 146*4882a593Smuzhiyun static-coefficient = <2427750>; 147*4882a593Smuzhiyun dynamic-coefficient = <4687>; 148*4882a593Smuzhiyun ts = <20000 2000 (-20) 2>; 149*4882a593Smuzhiyun thermal-zone = "gpu"; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun power_model@1 { 152*4882a593Smuzhiyun compatible = "arm,mali-g71-power-model"; 153*4882a593Smuzhiyun scale = <5>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun idvs-group-size = <0x7>; 157*4882a593Smuzhiyun l2-size = /bits/ 8 <0x10>; 158*4882a593Smuzhiyun l2-hash = /bits/ 8 <0x04>; /* or l2-hash-values = <0x12345678 0x8765 0xAB>; */ 159*4882a593Smuzhiyun}; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyungpu_opp_table: opp_table0 { 162*4882a593Smuzhiyun compatible = "operating-points-v2"; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun opp@533000000 { 165*4882a593Smuzhiyun opp-hz = /bits/ 64 <533000000>; 166*4882a593Smuzhiyun opp-microvolt = <1250000>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun opp@450000000 { 169*4882a593Smuzhiyun opp-hz = /bits/ 64 <450000000>; 170*4882a593Smuzhiyun opp-microvolt = <1150000>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun opp@400000000 { 173*4882a593Smuzhiyun opp-hz = /bits/ 64 <400000000>; 174*4882a593Smuzhiyun opp-microvolt = <1125000>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun opp@350000000 { 177*4882a593Smuzhiyun opp-hz = /bits/ 64 <350000000>; 178*4882a593Smuzhiyun opp-microvolt = <1075000>; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun opp@266000000 { 181*4882a593Smuzhiyun opp-hz = /bits/ 64 <266000000>; 182*4882a593Smuzhiyun opp-microvolt = <1025000>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun opp@160000000 { 185*4882a593Smuzhiyun opp-hz = /bits/ 64 <160000000>; 186*4882a593Smuzhiyun opp-microvolt = <925000>; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun opp@100000000 { 189*4882a593Smuzhiyun opp-hz = /bits/ 64 <100000000>; 190*4882a593Smuzhiyun opp-microvolt = <912500>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun}; 193*4882a593Smuzhiyun 194*4882a593SmuzhiyunExample for a Mali GPU with 2 clocks and 2 regulators: 195*4882a593Smuzhiyun 196*4882a593Smuzhiyungpu: gpu@6e000000 { 197*4882a593Smuzhiyun compatible = "arm,mali-midgard"; 198*4882a593Smuzhiyun reg = <0x0 0x6e000000 0x0 0x200000>; 199*4882a593Smuzhiyun interrupts = <0 168 4>, <0 168 4>, <0 168 4>; 200*4882a593Smuzhiyun interrupt-names = "JOB", "MMU", "GPU"; 201*4882a593Smuzhiyun clocks = <&clk_mali 0>, <&clk_mali 1>; 202*4882a593Smuzhiyun clock-names = "clk_mali", "shadercores"; 203*4882a593Smuzhiyun mali-supply = <&supply0_3v3>; 204*4882a593Smuzhiyun mem-supply = <&supply1_3v3>; 205*4882a593Smuzhiyun system-coherency = <31>; 206*4882a593Smuzhiyun operating-points-v2 = <&gpu_opp_table>; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyungpu_opp_table: opp_table0 { 210*4882a593Smuzhiyun compatible = "operating-points-v2", "operating-points-v2-mali"; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun opp@0 { 213*4882a593Smuzhiyun opp-hz = /bits/ 64 <50000000>; 214*4882a593Smuzhiyun opp-hz-real = /bits/ 64 <50000000>, /bits/ 64 <45000000>; 215*4882a593Smuzhiyun opp-microvolt = <820000>, <800000>; 216*4882a593Smuzhiyun opp-core-mask = /bits/ 64 <0xf>; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun opp@1 { 219*4882a593Smuzhiyun opp-hz = /bits/ 64 <40000000>; 220*4882a593Smuzhiyun opp-hz-real = /bits/ 64 <40000000>, /bits/ 64 <35000000>; 221*4882a593Smuzhiyun opp-microvolt = <720000>, <700000>; 222*4882a593Smuzhiyun opp-core-mask = /bits/ 64 <0x7>; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun opp@2 { 225*4882a593Smuzhiyun opp-hz = /bits/ 64 <30000000>; 226*4882a593Smuzhiyun opp-hz-real = /bits/ 64 <30000000>, /bits/ 64 <25000000>; 227*4882a593Smuzhiyun opp-microvolt = <620000>, <700000>; 228*4882a593Smuzhiyun opp-core-mask = /bits/ 64 <0x3>; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun}; 231*4882a593Smuzhiyun 232*4882a593SmuzhiyunExample for a Mali GPU supporting PBHA configuration via DTB (default): 233*4882a593Smuzhiyun 234*4882a593Smuzhiyungpu@0xfc010000 { 235*4882a593Smuzhiyun ... 236*4882a593Smuzhiyun pbha { 237*4882a593Smuzhiyun int_id_override = <2 0x32>, <9 0x05>, <16 0x32>; 238*4882a593Smuzhiyun propagate_bits = <0x03>; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun ... 241*4882a593Smuzhiyun}; 242