1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Hisilicon CPU controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Wei Xu <xuwei5@hisilicon.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The clock registers and power registers of secondary cores are defined 14*4882a593Smuzhiyun in CPU controller, especially in HIX5HD2 SoC. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun items: 19*4882a593Smuzhiyun - const: hisilicon,cpuctrl 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun reg: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun "#address-cells": 25*4882a593Smuzhiyun const: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun "#size-cells": 28*4882a593Smuzhiyun const: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun ranges: true 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunrequired: 33*4882a593Smuzhiyun - compatible 34*4882a593Smuzhiyun - reg 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunadditionalProperties: 37*4882a593Smuzhiyun type: object 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunexamples: 40*4882a593Smuzhiyun - | 41*4882a593Smuzhiyun cpuctrl@a22000 { 42*4882a593Smuzhiyun compatible = "hisilicon,cpuctrl"; 43*4882a593Smuzhiyun #address-cells = <1>; 44*4882a593Smuzhiyun #size-cells = <1>; 45*4882a593Smuzhiyun reg = <0x00a22000 0x2000>; 46*4882a593Smuzhiyun ranges = <0 0x00a22000 0x2000>; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun clock: clock@0 { 49*4882a593Smuzhiyun compatible = "hisilicon,hix5hd2-clock"; 50*4882a593Smuzhiyun reg = <0 0x2000>; 51*4882a593Smuzhiyun #clock-cells = <1>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun... 55