1*4882a593Smuzhiyun* QEMU Firmware Configuration bindings for ARM 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunQEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets 4*4882a593Smuzhiyunprovide the following Firmware Configuration interface on the "virt" machine 5*4882a593Smuzhiyuntype: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- A write-only, 16-bit wide selector (or control) register, 8*4882a593Smuzhiyun- a read-write, 64-bit wide data register. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunQEMU exposes the control and data register to ARM guests as memory mapped 11*4882a593Smuzhiyunregisters; their location is communicated to the guest's UEFI firmware in the 12*4882a593SmuzhiyunDTB that QEMU places at the bottom of the guest's DRAM. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunThe authoritative guest-side hardware interface documentation to the fw_cfg 15*4882a593Smuzhiyundevice can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunRequired properties: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- compatible: "qemu,fw-cfg-mmio". 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- reg: the MMIO region used by the device. 23*4882a593Smuzhiyun * Bytes 0x0 to 0x7 cover the data register. 24*4882a593Smuzhiyun * Bytes 0x8 to 0x9 cover the selector register. 25*4882a593Smuzhiyun * Further registers may be appended to the region in case of future interface 26*4882a593Smuzhiyun revisions / feature bits. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun/ { 31*4882a593Smuzhiyun #size-cells = <0x2>; 32*4882a593Smuzhiyun #address-cells = <0x2>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun fw-cfg@9020000 { 35*4882a593Smuzhiyun compatible = "qemu,fw-cfg-mmio"; 36*4882a593Smuzhiyun reg = <0x0 0x9020000 0x0 0xa>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun}; 39