1*4882a593Smuzhiyun========================================================= 2*4882a593SmuzhiyunSecondary CPU enable-method "nuvoton,npcm750-smp" binding 3*4882a593Smuzhiyun========================================================= 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunTo apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be 6*4882a593Smuzhiyundefined in the "cpus" node. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunEnable method name: "nuvoton,npcm750-smp" 9*4882a593SmuzhiyunCompatible machines: "nuvoton,npcm750" 10*4882a593SmuzhiyunCompatible CPUs: "arm,cortex-a9" 11*4882a593SmuzhiyunRelated properties: (none) 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunNote: 14*4882a593SmuzhiyunThis enable method needs valid nodes compatible with "arm,cortex-a9-scu" and 15*4882a593Smuzhiyun"nuvoton,npcm750-gcr". 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun cpus { 20*4882a593Smuzhiyun #address-cells = <1>; 21*4882a593Smuzhiyun #size-cells = <0>; 22*4882a593Smuzhiyun enable-method = "nuvoton,npcm750-smp"; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun cpu@0 { 25*4882a593Smuzhiyun device_type = "cpu"; 26*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 27*4882a593Smuzhiyun clocks = <&clk NPCM7XX_CLK_CPU>; 28*4882a593Smuzhiyun clock-names = "clk_cpu"; 29*4882a593Smuzhiyun reg = <0>; 30*4882a593Smuzhiyun next-level-cache = <&L2>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun cpu@1 { 34*4882a593Smuzhiyun device_type = "cpu"; 35*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 36*4882a593Smuzhiyun clocks = <&clk NPCM7XX_CLK_CPU>; 37*4882a593Smuzhiyun clock-names = "clk_cpu"; 38*4882a593Smuzhiyun reg = <1>; 39*4882a593Smuzhiyun next-level-cache = <&L2>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43