1*4882a593Smuzhiyun======================================================== 2*4882a593SmuzhiyunSecondary CPU enable-method "marvell,berlin-smp" binding 3*4882a593Smuzhiyun======================================================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThis document describes the "marvell,berlin-smp" method for enabling secondary 6*4882a593SmuzhiyunCPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should 7*4882a593Smuzhiyunbe defined in the "cpus" node. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunEnable method name: "marvell,berlin-smp" 10*4882a593SmuzhiyunCompatible machines: "marvell,berlin2" and "marvell,berlin2q" 11*4882a593SmuzhiyunCompatible CPUs: "marvell,pj4b" and "arm,cortex-a9" 12*4882a593SmuzhiyunRelated properties: (none) 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunNote: 15*4882a593SmuzhiyunThis enable method needs valid nodes compatible with "arm,cortex-a9-scu" and 16*4882a593Smuzhiyun"marvell,berlin-cpu-ctrl"[1]. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun cpus { 21*4882a593Smuzhiyun #address-cells = <1>; 22*4882a593Smuzhiyun #size-cells = <0>; 23*4882a593Smuzhiyun enable-method = "marvell,berlin-smp"; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cpu@0 { 26*4882a593Smuzhiyun compatible = "marvell,pj4b"; 27*4882a593Smuzhiyun device_type = "cpu"; 28*4882a593Smuzhiyun next-level-cache = <&l2>; 29*4882a593Smuzhiyun reg = <0>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun cpu@1 { 33*4882a593Smuzhiyun compatible = "marvell,pj4b"; 34*4882a593Smuzhiyun device_type = "cpu"; 35*4882a593Smuzhiyun next-level-cache = <&l2>; 36*4882a593Smuzhiyun reg = <1>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun-- 41*4882a593Smuzhiyun[1] arm/marvell,berlin.txt 42