1*4882a593Smuzhiyun======================================================== 2*4882a593SmuzhiyunSecondary CPU enable-method "al,alpine-smp" binding 3*4882a593Smuzhiyun======================================================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThis document describes the "al,alpine-smp" method for 6*4882a593Smuzhiyunenabling secondary CPUs. To apply to all CPUs, a single 7*4882a593Smuzhiyun"al,alpine-smp" enable method should be defined in the 8*4882a593Smuzhiyun"cpus" node. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunEnable method name: "al,alpine-smp" 11*4882a593SmuzhiyunCompatible machines: "al,alpine" 12*4882a593SmuzhiyunCompatible CPUs: "arm,cortex-a15" 13*4882a593SmuzhiyunRelated properties: (none) 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunNote: 16*4882a593SmuzhiyunThis enable method requires valid nodes compatible with 17*4882a593Smuzhiyun"al,alpine-cpu-resume" and "al,alpine-nb-service". 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun* Alpine CPU resume registers 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunThe CPU resume register are used to define required resume address after 23*4882a593Smuzhiyunreset. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunProperties: 26*4882a593Smuzhiyun- compatible : Should contain "al,alpine-cpu-resume". 27*4882a593Smuzhiyun- reg : Offset and length of the register set for the device 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun* Alpine System-Fabric Service Registers 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunThe System-Fabric Service Registers allow various operation on CPU and 33*4882a593Smuzhiyunsystem fabric, like powering CPUs off. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunProperties: 36*4882a593Smuzhiyun- compatible : Should contain "al,alpine-sysfabric-service" and "syscon". 37*4882a593Smuzhiyun- reg : Offset and length of the register set for the device 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyuncpus { 43*4882a593Smuzhiyun #address-cells = <1>; 44*4882a593Smuzhiyun #size-cells = <0>; 45*4882a593Smuzhiyun enable-method = "al,alpine-smp"; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun cpu@0 { 48*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 49*4882a593Smuzhiyun device_type = "cpu"; 50*4882a593Smuzhiyun reg = <0>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun cpu@1 { 54*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 55*4882a593Smuzhiyun device_type = "cpu"; 56*4882a593Smuzhiyun reg = <1>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun cpu@2 { 60*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 61*4882a593Smuzhiyun device_type = "cpu"; 62*4882a593Smuzhiyun reg = <2>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun cpu@3 { 66*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 67*4882a593Smuzhiyun device_type = "cpu"; 68*4882a593Smuzhiyun reg = <3>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyuncpu_resume { 73*4882a593Smuzhiyun compatible = "al,alpine-cpu-resume"; 74*4882a593Smuzhiyun reg = <0xfbff5ed0 0x30>; 75*4882a593Smuzhiyun}; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunnb_service { 78*4882a593Smuzhiyun compatible = "al,alpine-sysfabric-service", "syscon"; 79*4882a593Smuzhiyun reg = <0xfb070000 0x10000>; 80*4882a593Smuzhiyun}; 81