1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Calxeda Highbank L2 cache ECC 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun Binding for the Calxeda Highbank L2 cache controller ECC device. 11*4882a593Smuzhiyun This does not cover the actual L2 cache controller control registers, 12*4882a593Smuzhiyun but just the error reporting functionality. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunmaintainers: 15*4882a593Smuzhiyun - Andre Przywara <andre.przywara@arm.com> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun const: "calxeda,hb-sregs-l2-ecc" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun reg: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun interrupts: 25*4882a593Smuzhiyun items: 26*4882a593Smuzhiyun - description: single bit error interrupt 27*4882a593Smuzhiyun - description: double bit error interrupt 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunrequired: 30*4882a593Smuzhiyun - compatible 31*4882a593Smuzhiyun - reg 32*4882a593Smuzhiyun - interrupts 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunadditionalProperties: false 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunexamples: 37*4882a593Smuzhiyun - | 38*4882a593Smuzhiyun sregs@fff3c200 { 39*4882a593Smuzhiyun compatible = "calxeda,hb-sregs-l2-ecc"; 40*4882a593Smuzhiyun reg = <0xfff3c200 0x100>; 41*4882a593Smuzhiyun interrupts = <0 71 4>, <0 72 4>; 42*4882a593Smuzhiyun }; 43