1*4882a593SmuzhiyunBroadcom BCM63138 DSL System-on-a-Chip device tree bindings 2*4882a593Smuzhiyun----------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunBoards compatible with the BCM63138 DSL System-on-a-Chip should have the 5*4882a593Smuzhiyunfollowing properties: 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired root node property: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyuncompatible: should be "brcm,bcm63138" 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunAn optional Boot lookup table Device Tree node is required for secondary CPU 12*4882a593Smuzhiyuninitialization as well as a 'resets' phandle to the correct PMB controller as 13*4882a593Smuzhiyundefined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an 14*4882a593Smuzhiyun'enable-method' property. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired properties for the Boot lookup table node: 17*4882a593Smuzhiyun- compatible: should be "brcm,bcm63138-bootlut" 18*4882a593Smuzhiyun- reg: register base address and length for the Boot Lookup table 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties for the primary CPU node: 21*4882a593Smuzhiyun- enable-method: should be "brcm,bcm63138" 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional properties for the secondary CPU node: 24*4882a593Smuzhiyun- enable-method: should be "brcm,bcm63138" 25*4882a593Smuzhiyun- resets: phandle to the relevant PMB controller, one integer indicating the internal 26*4882a593Smuzhiyun bus number, and a second integer indicating the address of the CPU in the PMB 27*4882a593Smuzhiyun internal bus number. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun cpus { 32*4882a593Smuzhiyun cpu@0 { 33*4882a593Smuzhiyun compatible = "arm,cotex-a9"; 34*4882a593Smuzhiyun reg = <0>; 35*4882a593Smuzhiyun ... 36*4882a593Smuzhiyun enable-method = "brcm,bcm63138"; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun cpu@1 { 40*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 41*4882a593Smuzhiyun reg = <1>; 42*4882a593Smuzhiyun ... 43*4882a593Smuzhiyun enable-method = "brcm,bcm63138"; 44*4882a593Smuzhiyun resets = <&pmb0 4 1>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun bootlut: bootlut@8000 { 49*4882a593Smuzhiyun compatible = "brcm,bcm63138-bootlut"; 50*4882a593Smuzhiyun reg = <0x8000 0x50>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun======= 54*4882a593Smuzhiyunreboot 55*4882a593Smuzhiyun------ 56*4882a593SmuzhiyunTwo nodes are required for software reboot: a timer node and a syscon-reboot node. 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunTimer node: 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun- compatible: Must be "brcm,bcm6328-timer", "syscon" 61*4882a593Smuzhiyun- reg: Register base address and length 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunSyscon reboot node: 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunSee Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the 66*4882a593Smuzhiyundetailed list of properties, the two values defined below are specific to the 67*4882a593SmuzhiyunBCM6328-style timer: 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun- offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register 70*4882a593Smuzhiyun from the beginning of the TIMER block 71*4882a593Smuzhiyun- mask: Should be 1 for the SoftRst bit. 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunExample: 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun timer: timer@80 { 76*4882a593Smuzhiyun compatible = "brcm,bcm6328-timer", "syscon"; 77*4882a593Smuzhiyun reg = <0x80 0x3c>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun reboot { 81*4882a593Smuzhiyun compatible = "syscon-reboot"; 82*4882a593Smuzhiyun regmap = <&timer>; 83*4882a593Smuzhiyun offset = <0x34>; 84*4882a593Smuzhiyun mask = <0x1>; 85*4882a593Smuzhiyun }; 86