1*4882a593Smuzhiyun* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores 4*4882a593Smuzhiyunwith a shared L3 memory system, control logic and external interfaces to 5*4882a593Smuzhiyunform a multicore cluster. The PMU enables to gather various statistics on 6*4882a593Smuzhiyunthe operations of the DSU. The PMU provides independent 32bit counters that 7*4882a593Smuzhiyuncan count any of the supported events, along with a 64bit cycle counter. 8*4882a593SmuzhiyunThe PMU is accessed via CPU system registers and has no MMIO component. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun** DSU PMU required properties: 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- compatible : should be one of : 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun "arm,dsu-pmu" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- interrupts : Exactly 1 SPI must be listed. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- cpus : List of phandles for the CPUs connected to this DSU instance. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun** Example: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyundsu-pmu-0 { 24*4882a593Smuzhiyun compatible = "arm,dsu-pmu"; 25*4882a593Smuzhiyun interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; 26*4882a593Smuzhiyun cpus = <&cpu_0>, <&cpu_1>; 27*4882a593Smuzhiyun}; 28