1*4882a593SmuzhiyunAPM X-GENE SoC series SCU Registers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis system clock unit contain various register that control block resets, 4*4882a593Smuzhiyunclock enable/disables, clock divisors and other deepsleep registers. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunProperties: 7*4882a593Smuzhiyun - compatible : should contain two values. First value must be: 8*4882a593Smuzhiyun - "apm,xgene-scu" 9*4882a593Smuzhiyun second value must be always "syscon". 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - reg : offset and length of the register set. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample : 14*4882a593Smuzhiyun scu: system-clk-controller@17000000 { 15*4882a593Smuzhiyun compatible = "apm,xgene-scu","syscon"; 16*4882a593Smuzhiyun reg = <0x0 0x17000000 0x0 0x400>; 17*4882a593Smuzhiyun }; 18