1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Altera SOCFPGA Clock Manager 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Dinh Nguyen <dinguyen@kernel.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: test 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunproperties: 15*4882a593Smuzhiyun compatible: 16*4882a593Smuzhiyun items: 17*4882a593Smuzhiyun - const: altr,clk-mgr 18*4882a593Smuzhiyun reg: 19*4882a593Smuzhiyun maxItems: 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunrequired: 22*4882a593Smuzhiyun - compatible 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunadditionalProperties: false 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunexamples: 27*4882a593Smuzhiyun - | 28*4882a593Smuzhiyun clkmgr@ffd04000 { 29*4882a593Smuzhiyun compatible = "altr,clk-mgr"; 30*4882a593Smuzhiyun reg = <0xffd04000 0x1000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun... 34